Bus system and bus sense amplifier with precharge means

Details Bus system and bus sense amplifier with precharge means Bus system and bus sense amplifier with precharge means

1995-08-31

1997-08-26

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326 86, H03K 190185

Patent

active

056614179

ABSTRACT:
A purpose of this invention is to realize a bus system of high speed and low power consumption type applying precharge. A precharge signal input line (4), a power source potential (V.sub.DD), and a bus (1) are connected to a gate electrode, a drain region, and a source region of a first MOS transistor (MNP), the power source potential (V.sub.DD), a node (N1), and the bus (1) are connected to a gate electrode, a drain region, and a source region of a second MOS transistor (MN1), and the precharge signal input line (4) through an inverter (3), the power source potential (V.sub.DD), and the node (N1) are connected to a gate electrode, a source region, and a drain region of a third MOS transistor (MP1), respectively. In precharge period (PC=H), the potential of the bus (BUS) rises gradually, and the both transistors (MNP, MN1) are turned off. In EVL period (PC=L), when data is output from a register (6), the potential of the bus (BUS) drops, and the second MOS transistor (MN1) is turned on.

REFERENCES:
patent: 4857764 (1989-08-01), Young
patent: 4883989 (1989-11-01), Mizukami
patent: 4918329 (1990-04-01), Milby
patent: 5030857 (1991-07-01), Sanwo
patent: 5105104 (1992-04-01), Eisele
Proceedings of The IEEE 1994, Custom Integrated Circuits Conference, pp. 637-640, May 1-4, 1994, Harufusa Kondoh, et al., "An Efficient Self-Timed Queue Architecture For ATM Switch LSI's".

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