Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-02-17
2001-07-17
Etienne, Ario (Department: 2155)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C710S240000
Reexamination Certificate
active
06263393
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a bus switch which is provided in a computer in order to realize bus transaction across two or more buses.
Description of the Prior Art
A computer is generally provided with a bus switch in order to realize bus transaction (transfer of control signals (commands), data, etc.) across two or more buses. One or more devices (CPU, memory, an HDD via a slot, a modem via a slot, etc.) are connected to a bus, and such buses are connected together by the bus switch. Data which occurred on a bus (i.e. data which is transmitted by a device that is connected to the bus) is transferred to another bus by the bus switch.
A bus switch typically includes two or more bus bridges, a switch module (a crossbar switch) and a scheduler. Each bus bridge is connected to a corresponding bus in a one-to-one correspondence. In some types of bus switches, the bus bridge converts an address and/or a command and/or data on the bus into one or more cells. The cell generated by the bus bridge is temporarily stored in a cell buffer of the bus bridge, and transmitted to the switch module after transfer permission is given to the cell by the scheduler. The switch module is provided with two or more input ports and two or more output ports. Each input port of the switch module is connected to a corresponding bus bridge in a one-to-one correspondence, and each output port of the switch module is connected to a corresponding bus bridge in a one-to-one correspondence. The switch module transfers the cell from one of its input ports (to which the cell is supplied) to one of its output ports. The cell outputted from the output port is supplied to another bus bridge that corresponds to the output port. The bus bridge converts the cell into an address and/or a command and/or data, and transmits them to a bus that is connected to the bus bridge.
An example of a conventional bus switch is described in a document: Robert W.Horst, “TNet: A Reliable System Area Network”, IEEE Micro, February 1995, pages 37-45 (hereafter, referred to as “document No. 1”). Also in the conventional bus switch described in the document No. 1, a scheduler gives transfer permission to a cell which has been stored in a cell buffer, and supplies a control signal to a switch module (crossbar switch) and thereby connects a permitted transfer path in the switch module.
In such a bus switch, a transaction cell is provided with a delimiter, which is a word that indicates the end of the transaction cell, to its end. The switch module of the bus switch judges that the transaction cell has passed the switch module by detecting the delimiter. When the delimiter is detected, the switch module releases the transfer path which has been assigned to the transaction cell, and requests next scheduling to the scheduler.
When the number of buses connected to the bus switch has to be increased, the number of the bus bridges in the bus switch has to be increased according to the number of the buses, and the number of ports of the switch module has to be increased according to the number of the bus bridges. In order to increase the number of output ports of the switch module of the bus switch, many stages of crossbar switches used to be connected together, for example, as described in the document No. 1and a document: Bob Blau, Barry Isenstein, “A Transparent Switching Fabric for PCI”, HOT Interconnects IV, Aug. 15-17, 1996, pages 215-219.
The bus switch is also needed to transfer interrupt signals as well as the transaction cells. In some types of conventional bus switches, special-purpose interrupt signal lines are used specifically for transferring the interrupt signals, in the same way as a device which is described in U.S. Pat. No. 5,283,904.
After a cell passed the switch module, a transfer path which has been assigned to the cell has to be released and the next assignment of a transfer path in the switch module has to be started. For this, the switch module detects a transfer request which is sent from a bus bridge and informs the scheduler about the transfer request. Or a bus bridge that has received a cell via the switch module informs a control section of the switch module about completion of cell reception and its free buffer capacity, as described in the document No. 1.
In a switch module that is designed to execute switching and transfer of cells, an address and/or a command and/or data which are driven on a bus are packed into one or more cells and the cells are supplied to the switch module. The switch module transfers each cell to a destination output port of the cell, in units of cells. Therefore, a cell is transferred in the switch module as a single unit. In the conventional bus switch described in the document No. 1, a switch module executes switching and transfer in units of cells (packets) each of which including a header, an address, data and an error correction signal.
There exist several types of cells to be transferred by the switch module in the bus switch, such as transaction cells, bus control signal cells, scheduling cells, etc. Generally, these cells are not divided according to the type of cells and transferred by a common switch module and lines, as described in U.S. Pat. No. 5,255,265 and U.S. Pat. No. 5,267,235.
In a switch module of such conventional bus switches, a cell inputted to an input port of the switch module is necessarily transferred to one of the output ports of the switch module, regardless of whether the cell has been given a transfer permission by the scheduler or not, as described in U.S. Pat. No. 5,255,265 and U.S. Pat. No. 5,267,235.
The conventional bus switches described above involves the following problems or drawbacks.
First, the scheduler for assigning a transfer path to a cell directly controls connection of the transfer path in the switch module. Therefore, the scheduler and the switch module have to be connected via lines, or the scheduler and the switch module have to be formed on one LSI. In the case where the scheduler and the switch module are formed on one LSI, the number of buses which are connected to the bus switch can not be increased much, since the number of buses is limited by the number of gates and the number of pins of the LSI. On the other hand, in the case where the scheduler and the switch module are connected via lines, large bit width or band width of the lines becomes necessary, and thus design and construction of the bus switch becomes difficult.
Second, in the conventional bus switch in which the transaction cells, the bus control signal cells and the scheduling cells are not divided according to the type and transferred by a common switch module and lines, transfer of the bus control signal cells and the scheduling cells decreases the bandwidth of the line between the bus bridge and the switch module, thereby transfer throughput of the transaction cells via the line between the bus bridge and the switch module is necessitated to be decreased.
Third, in the conventional bus switches, a transfer path which has been set in the switch module is released when a delimiter (i.e. a word which indicates the end of a transaction cell) of a cell is detected, and then next scheduling is requested to the scheduler. However, some time period is necessary from the detection of the delimiter and completion of the next scheduling by the scheduler, and no transfer path can be utilized in the switch module during the time period. By this, the availability of the switch module has to be lowered and the throughput of the bus switch has to be decreased.
Fourth, as mentioned above, many-stage-connection of crossbar switches has to be employed in order to increase the number of buses connected to the bus switch. However, for the many-stage connection of crossbar switches, buffers have to be provided between the crossbar switches and flow control between the crossbar switches has to be executed. Further, the scheduler has to execute assignment of transfer paths across two or more crossbar switches, and thus complex algorithm and long processing time
Funaya Koichi
Kaneda Satoru
Etienne Ario
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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