Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-11-02
2004-08-03
Lefkowitz, Sumati (Department: 2189)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S305000, C710S065000, C370S222000, C370S402000, C709S251000
Reexamination Certificate
active
06772269
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an adapter for bus switch, a bridge for bus switch, and a bus switch and a bus switch system. More particularly, to a bus switch and system, that control, the data transfer on a ring bus with multiple I/O (input/output) ports or data transfer between multiple ring buses.
BACKGROUND OF THE INVENTION
A conventional data transfer system is composed so that multiple nodes are connected with a bus that allows the two-way communication of data, the nodes, respectively, are connected with multiple modules that conduct different processing, and the data transfer from one module to the other module is conducted. However, in this data transfer system, since data flows in the two directions, the switching control in data transfer such as switching of transfer direction and switching of source and destination, and the extraction of transfer timing are complicated. Therefore, it is difficult to enhance the transfer speed.
Japanese patent application laid-open No. 11-177560 (1999) discloses a data transfer system that enables data to flow in the single direction on the bus.
FIG. 1
shows the data transfer system disclosed in the Japanese patent application laid-open No. 11-177560. In
FIG. 1
, adapters
902
a
to
902
d
are inserted into multiple positions on a ring bus, and the adapters, respectively, are connected with modules
903
a
to
903
d
that conduct different processing. The modules
903
a
to
903
d,
respectively, conduct various processing, e.g., processing of audio data, processing of image data, input/output processing with the outside of integrated circuit.
The bus
901
has an n bit (n is a natural number) bus width, which is the same as the bit width of data to be transferred. Since the bus
901
is connected in the form of a ring, data is sent, in sequence, from the adapter
902
a
to the adapter
902
b,
and then from the adapter
902
b
to the adapter
902
c,
and is returned to the adapter
902
a
from the adapter
902
d.
Thus, since data is transferred in the one direction (single direction) on the ring bus
901
. The switch control of transfer becomes very easy.
FIG. 2
shows one adapter
902
in FIG.
1
. Since the adapters
902
a
to
902
d
have the same composition, one adapter
902
is explained below taking as an example. The adapter
902
is composed of a flip flop
1001
(D-type flip flop), a data extract/insert circuit
1002
that is connected with the flip flop
1001
, a selector
1003
that is connected with the flip flop
1001
and the data extract/insert circuit
1002
, and a flip flop
1004
(D-type flip flop) that is connected with the selector
1003
.
The flip flop
1001
temporarily stores data to be input from the adjacent adapter (at the previous stage in transfer sequence). The data extract/insert circuit
1002
judges whether the data being input from the flip flop
1001
is addressed to the module
903
connected therewith or not. If the data is sent to the module
903
, the data extract/insert circuit
1002
extracts the data, or inserts data when the module
903
thereof outputs the data. The selector
1003
selectively outputs the data from the flip flop
1001
or the data output from the data extract/insert circuit
1002
, to the next stage adapter. The selector
1003
has a function to judge whether data being input is addressed to the module connected to itself (its own adapter) or not, a function to send the data to the module connected when the data is addressed to itself and a function to insert data into a time slot transmittable when the data is output from the module connected to itself. The flip flop
1004
holds, with the system clock, data to be output to the bus
901
as the transmission line, and then outputs it to the bus
901
.
Data to be transferred through the circuit in
FIG. 3
is composed of “data entity”, “flag” (to indicate the validity or invalidity of data) added to the head, “destination ID”, and “classification”. The data extract/insert circuit
1002
reads the fields of “flag” and “destination ID” in data, thereby it judges whether data being input is addressed to its own module. When the data input to the flip flop
1001
is addressed to the module
903
of its own, it is transferred to the module
903
. When there is data to be output from the module
903
to the bus
901
, it conducts the switch control of the selector
1003
so that the module
903
and the flip flop
1004
are communicated with each other.
The operation of the data transfer system having the composition shown in
FIGS. 1 and 2
is explained below.
Data output from the flip flop
1004
for re-timing of the adapter
902
a
is taken into the input-side flip flop
1001
of the next-stage adapter
902
b
at the next transition timing of system clock. The data taken into the flip flop
1001
is input to the data extract/insert circuit
1002
. The data extract/insert circuit
1003
judges, based on the content of the flag and destination ID, whether the data is sent to its own module or not. In this judgement, when it is sent to the module of its own, the type of data is analyzed based on the “classification” field added to the data, and the data is sent to the module. Simultaneously, when there is a data to be transferred to the other module from the module of its own, “classification” field and “destination ID” of a module to receive the data are added to the data. Then, setting “flag” to indicate that the data is valid, the data is output to the selector
1003
. Also, even when there is no data to be transferred, if there is a transferred data in the module of its own, the flag of the data is removed and the data is, as a invalid data, output to the selector
1003
. As described above, the data extract/insert circuit
1002
takes data from the flip flop
1001
when its own module
903
is the destination, and switches the selector
1003
to transfer the data from the module
903
to the flip flop
1004
when its own module
903
is the source. Furthermore, when the module
903
is not related to the input/output of data, it switches the input of the selector
1003
to the flip flop
1001
, thereby data form the flip flop
1001
is passed toward the flip flop
1004
. Data from the flip flop
1004
is input to the next-stage adapter
902
c.
The other adapters operate in like manner.
Thus, by conducting the data transfer between the flip flop of an adapter and the flip flop of another adapter, the transfer switching control and the extraction of timing can be simplified. In addition, the data transfer between modules can be performed faster.
However, in the conventional data transfer system, when the number of modules connected to one ring bus increases, since the transfer bandwidth (data transfer amount per unit time) of each module is in reverse proportion to the number of modules, the transfer bandwidth of each module becomes small. Also, when the data processing speed of each module cannot follow the data transfer amount, it is necessary to reduce the data transfer speed. Thereby, the efficiency in data transfer lowers.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a bus switch adapter, a bus switch bridge, a bus switch and a bus switch system that increases the transfer bandwidth of each module (I/C port) thereby increasing the amount of data transferred per unit time.
It is a further object of the invention to provide a bus switch adapter, a bus switch bridge, a bus switch and a bus switch system that, even when the data processing speed of each module cannot follow the data transfer amount, it is not necessary to lower the data transfer speed.
1) According to the invention, a bus switch adapter for conducting one selected from a data taking operation that extracts data being transferred on a data transferring bus to take the data into a module such as an operating circuit and a transmit/receive circuit, a data inserting operation that inserts data output from the module into the data transferring bus, and a data transferring operation that transfers data
Dickstein Shapiro Morin & Oshinsky LLP.
Lefkowitz Sumati
NEC Corporation
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