Bus speed controller using switches

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus expansion or extension

Reexamination Certificate

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Details

C710S306000, C710S002000

Reexamination Certificate

active

06799238

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to computer busses, and in particular to a bus speed controller utilizing switches.
BACKGROUND OF THE INVENTION
A PCI bus in personal computer has a number of slots for plugging in PCI compatible cards. The speed of the bus depends on the number of slots. For the next version of the PCI bus, referred to as PCI-X, the bus speed is also based on the number of physical slots. The PCI-X bus may operate in a PCI-X bus mode or a PCI bus mode. The PCI bus mode supports older PCI cards, and is not generally as fast as PCI-X bus mode, which supports PCI-X bus cards operable at faster rates. Operating a PCI-X bus in PCI mode allowed up to four slots, each operating at 33 MHz, or two slots at 66 MHz. In PCI-X mode, four slots at 66 MHz, two at 100 MHz, or one slot operating at 133 MHz is allowed. In either mode, the maximum speed for the bus is defined by the number of slots provided and the ability of all cards to operate at that speed. Since the PCI bus only operated at a maximum of 66 MHz, PCI cards are generally only capable of operating at 33 MHz or 66 MHz. PCI-X cards are operable at both PCI card speeds, plus 100 MHz or 133 MHz. This allows PCI-X cards to operate on a PCI bus.
Basing bus speed on the number of slots provided allows little flexibility when operating the computer. A user may decide that they desire to use only one of the slots, yet if four slots are provided, they may be limited to operating that slot at only 33 or 66 MHz, even though the card is PCI-X compatible, and capable of running at 133 MHz. Similarly, a computer configured with only a single slot limits a user to using only a single slot. It is difficult to provide flexibility given the current fixed data bus rates available.
SUMMARY OF THE INVENTION
Switches are used to serially isolate connectors for peripheral devices on a bus. Bus speed is selected based on the number of peripheral devices coupled to the bus via the connectors. Switches are used in the bus to provide selected isolation of the connectors. In one embodiment, the bus is able to operate at higher speeds when fewer connectors are on the bus.
A method of configuring the bus determines how many devices are coupled to connectors on the bus. Portions of the bus not having devices coupled to connectors are isolated by controlling the switches between on and off states. Isolating connectors in this manner enables variation in the speed at which the bus operates. Generally, with fewer visible connectors, the bus is allowed to run at a faster speed. The speed is generally limited in one embodiment by the lowest maximum speed of each of the devices coupled to the bus via the connectors.


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patent: 6519669 (2003-02-01), Yanagisawa

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