Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2002-04-25
2004-09-14
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S046000, C326S058000
Reexamination Certificate
active
06791357
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a bus signal hold cell, a bus system with such a cell, and a method for operating the bus signal hold cell.
It is generally known that busses and bus systems are produced by interconnecting distributed information sources (transmitters) and sinks (receivers) via decentralized multiplexers and gate circuits. A bus system is thus a device which mediates the data exchange between the subscribers which are connected to the bus.
Functionally, a bus is a node with switches and taps in a star configuration. Technically, a bus system consists of at least one bus line and a plurality of subscribers that are connected to the line or lines. On the basis of the multiplexer function of the bus, only one subscriber (source) may ever transmit, i.e. switch data onto the bus. To this end, with the exception of the output of the subscriber sending the data, the outputs of all remaining subscribers are switched into the high-resistance state. This makes possible a very simple and flexible data intercommunication of the subscribers which are connected to the bus system.
In case no data are presently being written onto the bus, the outputs of all connected subscribers are switched into a high-resistance state. To this end, the bus includes a termination device which holds the last item of data that was driven over the bus whenever the outputs of all subscribers are in a state of high resistance.
Such a bus termination device can be realized in the form of a terminating resistor—for instance a transistor which is constructed as a high-side or low-side switch. Such pull-up or pull-down transistors are very compact and require only a small space on the chip because of their small number of components. In any case, such terminating resistors have an additional leakage current to ground, which leads to an undesirable dissipation. If this leakage current and the associated dissipation were negligible in earlier bus systems, they now play a larger, predominant role given the progressive integration density in integrated circuits and the trend toward ever smaller operating voltages relative to the occupied chip area.
Highly complex bus systems in scan-based integrated semiconductor circuits, in particular, often include a bus signal hold cell that is provided with a storage element having a weak driving capacity as the terminating device for a bus line.
FIG. 1
represents a basic circuit diagram of such a bus signal hold cell
2
that is connected to a bus line
1
. The bus signal hold cell
2
here includes two drivers
3
,
4
which are constructed as inverters, whose outputs control each other's inputs, respectively. When there are no longer any subscribers authorized to write, the last signal driven over the bus line
1
is held at the last logic state by the second driver
4
.
In contrast to the bus termination devices that are high-side or low-side switches, a bus signal hold cell has a greater number of transistors, but these advantageously generate almost no dissipation in operation.
When a bus system has no bus termination device, the bus signals can float, i.e., can have an undefined potential. As a result, the respective transistors of the driver elements that are connected to the bus line could even blow out in extreme cases.
In order to test an integrated circuit, it is necessary to charge the bus lines of a bus with defined, i.e. strictly prescribed, signals (controllability) and to read back the results for further evaluation (observability). In the case of a bus signal hold cell that will be tested using an ATPG (Automatic Test Pattern Generation) tool, this controllability and observability, which are necessary for testing a module, are not supported in all cases. Thus, the bus signal hold cell should exhibit the last condition written over the bus, however, it is impossible to determine with absolute certainty which signal is actually stored in the bus signal hold cell. For instance, the bus signal hold cell could include a condition other than the last condition driven over the bus because of a defect of the bus line or the inverters of the bus signal hold cell. But this cannot be determined with a known bus signal hold cell. The reduced controllability and observability for testing the bus signal hold cell lead to a reduction of the test coverage of these modules, that is to say, an elevated testing expenditure.
Another problem arises with respect to the testability of a plurality of macros that are interconnected on the chip via bus lines. In many cases, these highly complex macromodules cannot control and observe the respective bus lines to which they are connected during a test operation. This, too, leads to a reduced test coverage for automatically generated test patterns for testing macros. Very often this automatic test pattern generation is even impossible, so that only manual test patterns are possible, whose generation, implementation and evaluation are very expensive.
In order to increase the controllability and observability of an integrated circuit—that is, a module of an integrated circuit—partially test-friendly design measures are coupled to the inputs and outputs, which should make it possible to test this module. These test devices, which nevertheless undesirably increase the expended chip area, also reduce the efficiency of the overall circuit arrangement.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated bus signal hold cell, a method for driving the bus signal hold cell, and an integrated bus which overcome the above-mentioned disadvantages of the prior art apparatus and methods of this general type.
In particular, it is an object of the invention to improve the testability of bus systems and bus lines of an integrated circuit.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated bus signal hold cell that includes: a common input/output for coupling with a bus line; and at least a first inverter and a second inverter for holding a last condition of the bus line. Each one of the first inverter and the second inverter has an output and an input. The output of the first inverter is coupled to the input of the second inverter, and the output of the second inverter is coupled to the input of the first inverter. The integrated bus signal hold cell also includes an additional input for inputting a defined test signal. The input of the first inverter is coupled with the input/output. The output of the second inverter is coupled with the input/output.
With the foregoing and other objects in view there is also provided, in accordance with the invention, an integrated bus system, with a bus including at least one bus line having a high-resistance state and a low-resistance state. At least one subscriber is connected to the bus line. The subscriber is writing and/or reading signals onto or from the bus line. At least one bus signal hold cell is connected to the bus line. The bus signal hold cell includes a common input/output coupled with the bus line, and at least a first inverter and a second inverter for holding a last logic state of the bus line. Each one of the first inverter and the second inverter has an output and an input. The output of the first inverter is coupled to the input of the second inverter. The output of the second inverter is coupled to the input of the first inverter. The bus signal hold cell also includes an additional input for inputting a defined test signal. The input of the first inverter is coupled with the input/output. The output of the second inverter is coupled with the input/output. The bus signal hold cell stores the last logic state on the bus line in the high-resistance state of the bus line.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a method for driving an integrated bus signal hold cell, which includes the steps of:
providing a bus line having a high-resistance state and a low resistance state;
pro
Caty Olivier
Schöber Volker
Chang Daniel
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
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