Electronic digital logic circuitry – Accelerating switching
Patent
1993-06-18
1995-10-24
Westin, Edward P.
Electronic digital logic circuitry
Accelerating switching
326 86, 327 66, H03K 190185
Patent
active
054613302
ABSTRACT:
An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell a the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.
REFERENCES:
patent: 4651036 (1987-03-01), Tallaron
patent: 4791326 (1988-12-01), Vajdic et al.
patent: 4920339 (1990-04-01), Friend et al.
patent: 4937474 (1990-06-01), Sitch
patent: 5019728 (1991-05-01), Sanwo et al.
patent: 5029284 (1991-07-01), Feldbaumer et al.
patent: 5030855 (1991-07-01), Leung
patent: 5151621 (1992-09-01), Goto
patent: 5235222 (1993-08-01), Kondoh et al.
Coyle Joseph P.
Gist William B.
Digital Equipment Corporation
Dricoll Benjamin D.
Fisher Arthur W.
Maloney Denis G.
Westin Edward P.
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