Bus sampling on one edge of a clock signal and driving on...

Details Bus sampling on one edge of a clock signal and driving on... Bus sampling on one edge of a clock signal and driving on...

2000-10-06

2004-01-13

Rinehart, Mark H. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

C710S025000

Reexamination Certificate

active

06678767

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to digital systems and, more particularly, to buses within digital systems.
2. Description of the Related Art
A bus is frequently used in digital systems to interconnect a variety of devices included in the digital system. Generally, one or more devices are connected to the bus, and use the bus to communicate with other devices connected to the bus. As used herein, the term “agent” refers to a device which is capable of communicating on the bus. The agent may be a requesting agent if the agent is capable of initiating transactions on the bus and may be a responding agent if the agent is capable of responding to a transaction initiated by a requesting agent. A given agent may be capable of being both a requesting agent and a responding agent. Additionally, a “transaction” is a communication on the bus. The transaction may include an address transfer and optionally a data transfer. Transactions may be read transactions (transfers of data from the responding agent to the requesting agent) and write transactions (transfers of data from the requesting agent to the responding agent). Transactions may further include various coherency commands which may or may not involve a transfer of data.
The bus is a shared resource among the agents, and thus may affect the performance of the agents to the extent that the bus may limit the amount of communication by each agent and the latency of that communication. Generally, a bus may be characterized by latency and bandwidth. The latency may be affected by the amount of time used to arbitrate for the bus and to perform a transaction on the bus. The bandwidth may be affected by the amount of information (e.g. bits or bytes) that may be transmitted per cycle, as well as the amount of time used to perform the transfer. Both latency and bandwidth may be affected by the physical constraints of the bus and the protocol employed by the bus.
For example, many bus protocols require two clock cycles for arbitration: the transmission of the requests for the bus during the first clock cycle and the determination of the grant (and transmittal of the grant, in a central arbitration scheme) during the second clock cycle. The transaction may be initiated by the agent receiving the grant during the third clock cycle. The clock cycles may each be a period of a clock signal associated with the bus. Similarly, most bus protocols are limited in the number of bytes of data which may be transferred per clock cycle (e.g. 8 bytes is typical). Accordingly, transferring a cache block of data (which tends to dominate the transfers performed in modern digital systems) requires multiple clock cycles (e.g. 4 clock cycles for a 32 byte cache block on an 8 byte bus).
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a system including one or more agents coupled to a bus. The agent may be coupled to receive a clock signal associated with the bus, and may be configured to drive a signal responsive to a first edge (rising or falling) of the clock signal and to sample signals responsive to the second edge. The sampled signals may be evaluated to allow for the driving of a signal on the next occurring first edge of the clock signal.
By using the first edge to drive signals and the second edge to sample signals, the amount of time dedicated for signal propagation may be one half clock cycle. Bandwidth and/or latency may be positively influenced. In some embodiments, protocols which may require multiple clock cycles on other buses may be completed in fewer clock cycles. For example, certain protocols which may require two clock cycles may be completed in one clock cycle. In one specific implementation, for example, arbitration may be completed in one clock cycle. Request signals may be driven responsive to the first edge of the clock signal and sampled responsive to the second edge. The sampled signals may be evaluated to determine an arbitration winner, which may drive the bus responsive to the next occurrence of the first edge.
In one specific implementation, the data bus may be sized to allow for a single cycle data transfer for even the largest sized data that may be transferred in one transaction. For example, the data bus may be sized to transfer a cache block per clock cycle. In one implementation, the bus and agents may be integrated onto a single integrated circuit. Since the bus is internal to the integrated circuit, it may not be limited by the number of pins which may be available on the integrated circuit. Such an implementation may be particularly suited to a data bus sized to allow single cycle data transfer. Additionally, differential pairs may be used for each signal or a subset of the bus signals. Differential signal may further enhance the frequency at which the bus may operate.
In one particular implementation, the bus may support coherency and out of order data transfers (with respect to the order of the address transfers). The bus may support tagging of address and data phases, for example, to match address and corresponding data phases.
Broadly speaking, a system is contemplated comprising a bus and an agent coupled to the bus and to receive a clock signal for the bus. The clock signal has a rising edge and a falling edge during use. The agent is configured to drive one or more signals on the bus responsive to a first edge of the rising edge or the falling edge, and is further configured to sample a value on the bus responsive to a second edge of the rising edge or the falling edge.
Additionally, a method is contemplated. A value is driven on a bus responsive to first edge of a rising edge or a falling edge of a clock signal for the bus. A value is sampled from the bus responsive to a second edge of the rising edge or the falling edge.


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