Electrical computers and digital data processing systems: input/ – Access arbitrating
Reexamination Certificate
2000-02-09
2003-05-27
Ray, Gopal C. (Department: 2781)
Electrical computers and digital data processing systems: input/
Access arbitrating
C710S113000, C710S241000
Reexamination Certificate
active
06571306
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of microprocessors and computer networks and, more particularly, to bus masters and bus protocols.
2. Description of the Related Art
While individual computers enable users to accomplish computational tasks which would otherwise be impossible by the user alone, the capabilities of an individual computer can be multiplied by using it in conjunction with one or more other computers. Individual computers are therefore commonly coupled together to form a computer network.
Computer networks may be interconnected according to various topologies. For example, several computers may each be connected to a single bus, they may be connected to adjacent computers to form a ring, or they may be connected to a central hub to form a star configuration. These networks may themselves serve as nodes in a larger network. While the individual computers in the network are no more powerful than they were when they stood alone, they can share the capabilities of the computers with which they are connected. The individual computers therefore have access to more information and more resources than standalone systems. Computer networks can therefore be a very powerful tool for business, research or other applications.
When multiple computers share a common bus, it becomes necessary to provide a mechanism for controlling access to that bus. Typically an arbitration scheme is used to control which device requiring access to the bus, or “bus master”, is granted control of the bus at any given time. Examples of bus masters may include microprocessors, I/O devices, communication devices and other devices capable of initiating transactions on a bus. Arbitration generally involves a bus master requesting access to the bus and a subsequent grant of access to the bus. Arbitration schemes may be either distributed or centralized. Once a bus master is granted control of the bus, it may begin its transaction. The process of arbitrating for control of the bus creates additional overhead for transactions which may reduce system performance. By eliminating the arbitration process, transaction overhead may be reduced and overall system performance improved. One method of eliminating bus arbitration is to use what is called bus “parking”. Bus parking involves allowing a particular bus master to have a default bus grant. This parked bus master may then initiate transactions without first arbitrating for bus access by issuing a bus request.
In some computer networks there may be devices connected to the common bus which are not required to arbitrate for access in the same manner as other bus masters. For example, a repeater may be able to issue a high priority request on a bus and be assured of gaining access without having to arbitrate. In such a case, the parked status of a bus master on the network may remain unchanged. One problem which may arise in such a computer network occurs when a device such as a repeater gains control of the bus and begins a stream of transactions, while at the same time a parked bus master requires access to the bus. However, a parked bus master will not issue a bus request and will not initiate a transaction while the repeater indicates a high priority transaction is in progress. Consequently, the repeater has no way of knowing that the bus master requires access to the bus. One possible solution to this problem involves stopping the repeater periodically to allow a parked bus master to initiate a transaction if necessary. However, such a solution may involve stopping transactions unnecessarily when no bus master requires access to the bus, reducing performance.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a bus master and method as described herein. When a parked bus master sees a threshold number of high priority transaction cycles, it issues a request for access to the bus. Advantageously, a high priority device may be made aware of the need for the bus by the parked bus master only when it is actually needed and system performance may be improved.
Broadly speaking, a computer network is contemplated comprising a plurality of bus masters coupled to a bus. A first bus master of the plurality of bus masters may be parked on the bus, and may assert a bus request, in response to detecting a threshold number of consecutive high priority cycles on the bus have been seen and the first bus master requires access to the bus. In addition, a high priority device is coupled to the bus which may inhibit the first bus master from beginning a transaction on the bus.
Also contemplated is a bus master comprising a counter and bus access circuitry. The counter counts the number of consecutive high priority cycles seen on the bus, while the bus access circuitry may assert a bus request, in response to the counter meeting a threshold number of consecutive high priority cycles on the bus and the bus master requires access to the bus.
Further contemplated is a method comprising parking a bus master on a bus, issuing a high priority transaction on the bus by a high priority device, and inhibiting the bus master from issuing a transaction on the bus by asserting an inhibit signal from the high priority device. Also, counting consecutive high priority cycles of the high priority transaction on the bus and issuing a first bus request, wherein the first bus request is issued by the bus master, in response to detecting a threshold number of said consecutive high priority cycles on the bus have been seen and the bus master requires access to the bus.
REFERENCES:
patent: 5954809 (1999-09-01), Riley et al.
patent: 5983302 (1999-11-01), Christiansen et al.
patent: 6101570 (2000-08-01), Neumyer
patent: 6272580 (2001-08-01), Stevens et al.
PCI Local Bus Specification, Revision 2.2, Dec. 1998, pp. 1-6 and 46-74.
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Ray Gopal C.
Sun Microsystems Inc.
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