Bus repeater for coupling a first and second bus

Details Bus repeater for coupling a first and second bus Bus repeater for coupling a first and second bus

2005-01-04

2005-01-04

Ray, Gopal C. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S031000, C370S492000, C375S211000

Reexamination Certificate

active

06839789

ABSTRACT:
A bus-repeater for coupling at least one first bus with a second bus, by way of which data may be transmitted in the form of serial digital signal pulse sequences and including at least one first and a second transmit-receive device, with which the first and, respectively, the second bus may be coupled and by way of which the bus-repeater may transmit signal pulse sequences, received via the first bus on the second bus, and vice versa. In accordance with the invention the bus-repeater includes locking device, which during transmission of a signal pulse received from the first bus to the second bus lock transmission by the bus-repeater of signal pulses, received from the second bus, via the first bus for a transmission locking time and vice versa.

REFERENCES:
patent: 3673326 (1972-06-01), Lee
patent: 4974153 (1990-11-01), Pimm et al.
patent: 5809077 (1998-09-01), Dorner et al.
patent: 6493785 (2002-12-01), Galloway
patent: 6557064 (2003-04-01), Galloway
patent: 6581126 (2003-06-01), Regula
patent: 20010004751 (2001-06-01), Necker et al.
“Scalable coherent interface” by Gustavson, D.B. (abstract only).*
“IEEE P1596, a scalable coherent interface for gigabyte/sec multiprocessor applications” by Gustavson, D.B. (abstract only).

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