Bus protocol violation monitor systems and methods

Details Bus protocol violation monitor systems and methods Bus protocol violation monitor systems and methods

1997-08-15

1999-09-14

Ray, Gopal C.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Protocol

714 39, G06F 1300

Patent

active

059516615

ABSTRACT:
A computer system employing a bus protocol violation monitor system and method. The monitor system includes a bus wait timer logic circuit which comprises a state machine that receives a portion of the bus interface control signals, a programmable timer module and a plurality of data selectors that are actuatable responsive to a control input. In addition to storing the violation information in a register, the system provides for interrupts with graded levels of priorities.

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