Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol
Reexamination Certificate
2006-07-11
2006-07-11
Park, Ilwoo (Department: 2182)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Protocol
C710S107000, C710S100000, C710S305000, C326S034000
Reexamination Certificate
active
07076582
ABSTRACT:
A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.
REFERENCES:
patent: 4500988 (1985-02-01), Bennett et al.
patent: 4734909 (1988-03-01), Bennett et al.
patent: 4883989 (1989-11-01), Mizukami
patent: 5402379 (1995-03-01), McClure
patent: 5646556 (1997-07-01), Longwell et al.
patent: 5698995 (1997-12-01), Usami
patent: 5901097 (1999-05-01), Koshikawa
patent: 5919265 (1999-07-01), Nishtala et al.
patent: 6078546 (2000-06-01), Lee
patent: 6173349 (2001-01-01), Qureshi et al.
patent: 6378017 (2002-04-01), Girzon et al.
patent: 6418491 (2002-07-01), Martin San Juan
patent: 6442642 (2002-08-01), Brooks
patent: 6442644 (2002-08-01), Gustavson et al.
patent: 6601123 (2003-07-01), Zhang et al.
patent: 6643792 (2003-11-01), Kurosawa
patent: 2001/0034802 (2001-10-01), Peng et al.
patent: 2002/0147875 (2002-10-01), Singh et al.
Halfhill, “SiByte Reveals 64-Bit Core for NPUs,” Microprocessor Report, Jun. 2000, pp. 45-48.
Pentium® Pro Family Developer's Manual, vol. 1: Specifications, Chapter 3, pp. 1-25, 1996.
“PowerPC 601; RISC Microprocessor User's Manual,” IBM Microelectronics, Power PC, Motorola, Rev. 1, 1993, 8 pages.
SiByte, “Target Applications,” http://sibyte.com/mercurian/applications.htm, Jan. 15, 2001, 2 pages.
SiByte, “SiByte Technology,” http://sibyte.com/mercurian/technology.htm, Jan. 15, 2001, 3 pages.
SiByte, “The Mercurian Processor,” http://sibyte.com/mercurian, Jan. 15, 2001, 2 pages.
SiByte, “Fact Sheet,” SB-1 CPU, Oct. 2000, rev. 0.1, 1 page.
SiByte, “Fact Sheet,” SB-1250, Oct. 2000, rev. 0.2, 10 pages.
Stephanian, SiByte, SiByte SB-1 MIPS64 CPU Core, Embedded Processor Forum 2000, Jun. 13, 2000, 15 pages.
Jim Keller, “The Mercurian Processor: A High Performance, Power-Efficient CMP for Networking,” Oct. 10, 2000, 22 pages.
Cho James Y.
Pearce Mark H.
Rowlands Joseph B.
Broadcom Corporation
Garlick Harrison & Markison LLP
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