Bus precharge during a phase of a clock signal to eliminate...

Details Bus precharge during a phase of a clock signal to eliminate... Bus precharge during a phase of a clock signal to eliminate...

2006-07-11

2006-07-11

Park, Ilwoo (Department: 2182)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Protocol

C710S107000, C710S100000, C710S305000, C326S034000

Reexamination Certificate

active

07076582

ABSTRACT:
A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.

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