Bus precharge during a phase of a clock signal to eliminate...

Details Bus precharge during a phase of a clock signal to eliminate... Bus precharge during a phase of a clock signal to eliminate...

2001-05-15

2004-11-09

Park, Ilwoo (Department: 2182)

Electrical computers and digital data processing systems: input/

Intrasystem connection

C326S034000

Reexamination Certificate

active

06816932

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to systems and, more particularly, to buses within digital systems.
2. Description of the Related Art
A bus is frequently used in digital systems to interconnect a variety of devices included in the digital system. Generally, one or more devices are connected to the bus, and use the bus to communicate with other devices connected to the bus. As used herein, the term “agent” refers to a device which is capable of communicating on the bus. The agent may be a requesting agent if the agent is capable of initiating transactions on the bus and may be a responding agent if the agent is capable of responding to a transaction initiated by a requesting agent. A given agent may be capable of being both a requesting agent and a responding agent. Additionally, a “transaction” is a communication on the bus. The transaction may include an address transfer and optionally a data transfer. Transactions may be read transactions (transfers of data from the responding agent to the requesting agent) and write transactions (transfers of data from the requesting agent to the responding agent). Transactions may further include various coherency commands which may or may not involve a transfer of data.
The bus is a shared resource among the agents, and thus may affect the performance of the agents to the extent that the bus may limit the amount of communication by each agent and the latency of that communication. Generally, a bus may be characterized by latency and bandwidth. The latency may be affected by the amount of time used to arbitrate for the bus and to perform a transaction on the bus. The bandwidth may be affected by the amount of information (e.g. bits or bytes) that may be transmitted per cycle, as well as the amount of time used to perform the transfer. Both latency and bandwidth may be affected by the physical constraints of the bus and the protocol employed by the bus. When a bus is shared by more than one agent to transfer information, a transient collision may occur between a first agent driving the bus in a clock cycle and a second agent driving the bus in an immediately subsequent clock cycle. During the transient collision, both agents are driving the same lines. In order to avoid this transient collision, either an agent must delay driving the bus during a clock cycle that it is allowed to drive the bus, or an idle clock cycle must be added when the bus is to be driven by a different agent than the agent currently driving the bus. Either solution may negatively impact the latency and/or bandwidth of the bus.
SUMMARY OF THE INVENTION
A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in one clock cycle. Since the bus is driven only during the non-precharge period, the transient collision may be avoided without adding an idle cycle on the bus.
In one embodiment, the bus may employ differential pairs of lines for each signal. These differential pairs may be precharged and driven as mentioned above. Although the precharging occupies a portion of the clock cycle, the low signal swings allowed with the differential signalling may reduce the overall amount of time used to perform a transfer.
Broadly speaking, an apparatus is contemplated comprising a bus and a circuit coupled thereto. The bus includes at least one line. The circuit is further coupled to receive a clock signal for the bus, the clock signal having a rising edge and a falling edge during use. The circuit is configured to precharge the at least one line during at least a portion of a first interval of a period of the clock signal, the first interval being between an occurrence of a first edge of the rising edge or the falling edge and an occurrence of a second edge of the rising edge or the falling edge. A transfer occurs on the bus during a second interval of the period, wherein the second interval is exclusive of the first interval.
Additionally, a method is contemplated. At least one line of a bus is precharged during at least a portion of a first interval of a period of a clock signal for the bus. The clock signal has a rising edge and a falling edge during use. The first interval is between an occurrence of a first edge of the rising edge or the falling edge and an occurrence of a second edge of the rising edge or the falling edge. Transferring occurs on the bus during a second interval of the period, the second interval being exclusive of the first interval.


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