Bus power savings using selective inversion in an ECC system

Details Bus power savings using selective inversion in an ECC system Bus power savings using selective inversion in an ECC system

2002-09-06

2004-05-04

Moise, Emmanuel L. (Department: 2133)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S052000, C711S103000, C713S320000

Reexamination Certificate

active

06732288

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to bus power savings by using selective inversion technology in a system employing an error correction code (ECC) encoder.
2. Background Information
Electronic products may be thought of as those products that involve the controlled conduction of electrons or other charge carriers. Examples of electronic products include radios, desktop and laptop computers, work stations, and servers as well as those involved in high-end networking and storage technology. Just about all electronic products employ one or more microprocessors located on a printed circuit board. These microprocessors engage a computer operating system as well as applications.
Processors are conventionally coupled to a memory through a memory interface. Data is transferred from the processor to the memory through the memory interface where that data is stored in memory until requested. When that data is requested, the data is transferred from the memory by the processor. The process of transferring data to and from the memory requires time. As the time to transfer the data to and from the memory is decreased, processor speed is increased. Thus, it is highly desirable to increase the transfer speed of data to and from the memory.
Data is transferred within a computer in a signal composed of a string of logic one and logic zero bits whereby a one or zero represent the state of the logic of a single bit. Conventionally, zero volts represents a logic zero bit and five volts represents a logic one bit. In a string of logic one and logic zero bits, the numeric voltage change between an adjacent logic one and logic zero is referred to as the swing level. Since it takes less time to generate a small voltage change than it does to generate a large voltage change for a given loading, a universal approach to achieve higher data transfer speeds is to reduce signal swing level from five volts to something less.
Complementary Metal Oxide Semiconductor (CMOS) is a semiconductor fabrication technology using a combination of n- and p-doped semiconductor material to achieve low power dissipation. To achieve higher data transfer speeds in CMOS circuits, Gunning Transceiver Logic (GTL) is extensively used. GTL is a standard for electrical signals where the GTL signal represents the state of the logic of the data. In a GTL signal, the signal swings between 0.4 volts and 1.2 volts with a reference voltage centered about 0.8 volts (800 millivolts). Since only a deviation of at most about 0.4 volts from the central or reference voltage of 0.8 volts is required to drive the state of the logic from logic zero to logic one or logic one to logic zero, a GTL signal is a low voltage swing logic signal. GTL signaling may also be implemented as active low, whereby a low voltage (0.4V) is used to represent a logic one and a high voltage (1.2V) is used to represent a logic zero. Gunning Transceiver Logic has several advantages. The resistive termination of a GTL signal provides a clean signaling environment. Moreover, the low terminating voltage of 1.2 volts results in reduced voltage drops across the resistive elements. Thus, the primary advantage of a GTL signal is that it can operate at a very high frequency. Furthermore, since the swing is low, electromagnetic interference (EMI) can be contained.
A problem with GTL technology is the relatively high consumption of electrical power needed to operate GTL technology. A System using active low GTL technology consumes insignificant power when the state of the logic of the data signal is logic zero since the power used is negligible. However, when the state of the logic is logic one, the system consumes a large quantity of power. Rambus technology is similar to GTL technology in that Rambus systems, developed by Rambus, Inc. of Mountain View, Calif., consume significant power only when the signals are in one of the two logic states. Both Rambus and GTL technology systems may be view as power-on logic state systems as they both consume significant power when the logic is in one of two states.
Consumption of power translates into higher costs and diminishes the useful life of components within an electrical system. This is especially true for desktop and laptop personal computers. Thus, it is desirable to reduce the amount of power consumed by devices employing power-on logic state buses.
SUMMARY OF THE INVENTION
The present invention relates to an error correction and selective inversion circuit (ESIC). The ESIC includes a power-on logic state (POLS) bus having a data signal and an error code correction (ECC) generator having an input coupled to the POLS bus. The ECC generator includes one or more correction pins. The ESIC also includes an inversion generator having an input attached to the POLS bus in parallel with the ECC generator. The output of the inversion generator is integrated with the output of on or more correction pins from the ECC generator so as to form an inverted data signal output. An inverted data signal is recovered by the ESIC in an inversion recovery.


REFERENCES:
patent: 4661955 (1987-04-01), Arlington et al.
patent: 5644583 (1997-07-01), Garcia et al.
patent: 6292868 (2001-09-01), Norman
Mircea R. Stan & Wayne P. Burleson, “Bus-Inveert Coding for Low-Power I/O,” 3 IFEE Trans. On VLSI Systems 49 (Mar. 1995).
Mircea R. Stan, “Low Power Encoding for VLSI and ECC Duals”, 1998 IEEE International Symposium, pp. 19.

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