Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2000-12-19
2004-02-24
Lefkowitz, Sumati (Department: 2189)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S046000, C710S015000, C710S016000, C710S017000, C710S018000, C710S019000
Reexamination Certificate
active
06697900
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to computer systems, and more particularly to a new and improved bus monitor and method of monitoring the operation of an input/output (I/O) or peripheral bus and displaying information in real-time which describes the phases or operations performed by the bus, to enable a better understanding of the performance and activity on the bus.
BACKGROUND OF THE INVENTION
A communication bus in a computer system is a set of conductive wires that forms a transmission path for communicating data between components of the computer system. The conductive wires include address lines, data lines and control lines. Signals are asserted on the address, data and control lines during bus cycle intervals to communicate address, data and control and status signals between components of the computer system according to a bus protocol. The bus protocol describes the signals which control communication between components of the computer system. The bus protocol is implemented by the application of control signals during each bus cycle in which data, address and control and status information is communicated between the components connected to the bus. Communicating data typically requires many bus cycles to transfer the data between components, although the communication of address and control and status information may require only one bus cycle.
A SCSI bus is a well-known example of an I/O or peripheral bus used in a computer system. A SCSI bus includes many address and data lines and a lesser number of control lines. The control lines communicate different control and status messages or signals. The combination of control signals that are asserted on the control lines during each SCSI bus cycle form a SCSI bus phase. For example, the SCSI bus control signals include a request signal (REQ), an acknowledge signal (ACK), a busy signal (BSY), a selection signal (SEL), an attention signal (ATN), a message signal (MSG), a command signal (C_D), and an I/O signal (I_O). The SCSI bus phases include BUS FREE, ARBITRATION, SELECTION, RESELECTION, COMMAND, DATA, STATUS and MESSAGE. A COMMAND bus phase occurs when the MSG signal is in a low logic state, the C_D signal is in a high logic state, and the I_O signal is in a low logic state during a bus cycle. In the COMMAND phase, a command is sent from one component to another component connected to the bus. Data is transferred on data lines of the SCSI bus during the COMMAND, DATA, STATUS and MESSAGES phases, which are collectively termed the information transfer phases. The SCSI bus is never in more than one bus phase at a time during each bus cycle.
A bus monitor is used for monitoring signals asserted on an I/O or peripheral bus, such as a SCSI bus, used in a computer system. The bus monitor senses signals asserted during bus phases of activity occurring on the bus. The communication activity is then displayed so that it can be observed and analyzed by a user to determine whether the bus is operating properly and efficiently, and to identify problems which may be occurring on the bus or with the components which are connected to the bus.
One typical bus monitor is a trace analyzer program. The trace analyzer program generates a considerable amount of bus activity for a few seconds, and captures a history of the signals asserted on the bus during the few seconds of communication activity. The trace history is then analyzed to identify distinct bus phases comprising the captured signal activity, and to identify communications occurring during the bus phases identified. Since the trace analyzer program generates the bus activity, the generated activity is in many regards artificial because it does not represent the types of activity which may actually occur during realistic use of the computer system.
The trace analyzer can capture only a few seconds of bus communication activity at a time based on stimulation of a somewhat artificial nature, and it cannot display bus information continuously in real-time as would occur during realistic use of the bus in a fully-functional computer system. Any information captured by the trace analyzer must be processed, analyzed and displayed after the capture of information is complete. The trace analyzer must then be restarted to stimulate more activity and capture additional information caused by that stimulated activity. The resulting discontinuity with respect to the previous information captured does not reflect the intervening activity on the bus, thereby preventing real-time information from being obtained. The trace analyzer cannot display the current bus phase that is active on the bus, and cannot periodically and continuously display the percentages of activity associated with each distinct bus phase during the short monitoring period or over a longer time period. In general, the load, efficiency and performance of the bus cannot be observed in real-time using the trace analyzer because the trace analyzer does not produce immediate and continuous information.
These and other considerations that have given rise to the present invention.
SUMMARY OF THE INVENTION
One aspect of the present invention relates to monitoring activity of an I/O or peripheral bus and generating and displaying information describing bus information occurring in real-time during typical communication activity. Another aspect of the invention relates to displaying percentages of occurrences for bus phases that have been active during a predetermined sampling period. Another aspect of the invention relates to allowing a user to observe the load, efficiency and performance of the bus continuously in real-time by observing bus information derived from real-time, normal communication activity.
In accordance with these and other aspects, the present invention is directed to a bus monitor for monitoring bus phases of an I/O bus and generating bus information describing activity of the bus in real-time. The I/O bus has control lines upon which control signals which define bus phases are asserted during each cycle of bus activity. The bus monitor comprises a storage device connected to the control lines to sense the control signals asserted on the control lines and to store bus phase information describing the bus phases defined by the control signals. The bus monitor also includes a processor connected to the storage device and operative to retrieve the bus phase information from the storage device at a predetermined polling rate and to compute the bus information from the retrieved bus phase information. Preferably, a display presents the computed bus information.
In accordance with other aspects, the present invention also relates to a method of generating bus information in real-time which describes activity of an I/O bus during bus phases occurring in bus cycles. The method involves the steps of sensing signals asserted on the bus which define the bus phases, deriving bus phase information from the sensed signals, collecting the bus phase information during a sampling period which extends over a plurality of bus cycles, computing bus information using the bus phase information collected during the sampling period, and continuously repeating the sampling time periods. Other preferred aspects of the method include displaying the computed bus information after each sampling period, and storing the bus phase information in memory during each sampling period prior to computing the bus information.
These and other aspects of the present invention permit actual activity of the bus to be observed in real-time, thereby allowing the user to monitor the performance of the bus continuously and observe any problems which might negatively impact the performance of the bus.
REFERENCES:
patent: 5361346 (1994-11-01), Panesar et al.
patent: 5524268 (1996-06-01), Geldman et al.
patent: 5606673 (1997-02-01), Chounan
patent: 6243834 (2001-06-01), Garrett
patent: 08249246 (1996-09-01), None
“Phase-time measuring device for SCSI system bus”, Derwent-Acc-No. 1996-046996, Pub-No. JP 07311733A, Pub-Date Nov. 28, 1995.
Lefkowitz Sumati
LSI Logic Corporation
Suiter - West PC LLO
Vu Trisha
LandOfFree
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