Bus master transactions on a low pin count bus

Details Bus master transactions on a low pin count bus Bus master transactions on a low pin count bus

1997-09-24

2000-09-12

Ray, Gopal C.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710 22, G06F 1300, G06F 1328

Patent

active

061191892

ABSTRACT:
A system including a host, a peripheral controller device, and a bus master device each coupled to a bus having a plurality of general purpose signal lines for carrying time-multiplexed address, data, and control information. The bus master device communicates with the host and the peripheral controller device via the bus.

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