Bus-line midpoint holding circuit for high speed memory read ope

Details Bus-line midpoint holding circuit for high speed memory read ope Bus-line midpoint holding circuit for high speed memory read ope

1999-03-22

2000-08-01

Nelms, David

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

36518905, G11C 700

Patent

active

06097642&

ABSTRACT:
In a memory system, sense amplifiers are connected to a memory cell array for driving a number of read bus lines according to data read from the memory cell array at periodic intervals. A number of midpoint holding circuits are associated respectively with the read bus lines. Each of the midpoint holding circuits comprises a pull-up driver and a pull-down driver connected in series between terminals of high and low voltages, a circuit node between the drivers being connected to the associated bus line, the drivers having a substantially equal threshold voltage. Control circuitry is responsive to a midpoint control pulse for causing one of the drivers to turn on depending on a voltage at the bus line, so that the conducting driver automatically turns off when the bus line attains a midpoint level between the high and low voltages during an interval when the bus line is not driven by the sense amplifiers.

REFERENCES:
patent: 5729152 (1998-03-01), Leung et al.
patent: 5751978 (1998-05-01), Tipple

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