Bus line current calibration

Details Bus line current calibration Bus line current calibration

2000-11-13

2003-04-08

Assouad, Patrick (Department: 2857)

Data processing: measuring, calibrating, or testing

Measurement system in a specific environment

Electrical signal parameter measurement system

C327S108000, C326S062000, C326S080000

Reexamination Certificate

active

06546343

ABSTRACT:

TECHNICAL FIELD
This invention relates to bus systems in which line voltages are generated by varying line currents and are interpreted with reference to a reference voltage.
BACKGROUND OF THE INVENTION
FIG. 1
is a block diagram showing a high-speed digital computer bus system
20
. The bus system includes a number of discrete devices
22
-
24
, which communicate over an electrical bus
25
at very high speeds. The bus includes a plurality of data transmission lines.
This system includes a master device
22
and a plurality of slave devices
23
-
24
. The master device
22
initiates and controls data exchanges over bus
25
. During a data exchange, any one of devices
22
-
24
can act as either a transmitting component or a receiving component. Generally, there is only one transmitting component during any single data exchange. However, there can be one or a is plurality of receiving components during a data exchange.
FIG. 2
illustrates the configuration and operation of a single bus line
26
between a transmitting component
27
and a receiving component
28
. The bus line is terminated at one end to a termination voltage V
term
through a termination impedance R
term
. Transmitting component
27
has a line current driver
29
, which produces line voltages with specified relationships to a reference voltage VREF.
More specifically, driver
29
is a current source or sink that creates desired voltage drops across termination impedance R
term
. The current driver
29
is turned on or otherwise enabled to produce one logic level voltage, and is turned off or otherwise disabled to produce another logic level voltage. In actual embodiment, the current driver
29
sinks current when enabled, and does not sink or source current when disabled. When disabled, the line voltage is approximately equal to V
term
. When enabled, the line voltage is lower than V
term
, because of a voltage drop through termination impedance R
term
.
As an example, suppose that V
term
is 2.5 volts. When driver
29
is disabled there is no current through the bus line, and the bus line voltage is equal to V
term
, or 2.5 volts. This is the high logic level, and is referred to as V
OH
. On the other hand, when driver
29
is enabled the current through the bus line drops the line voltage to a lower value V
OL
, which in this example is 1.9 volts. V
OL
is the low logic level.
The voltage difference between V
OH
and V
OL
, also referred to as a line voltage swing V
swing
, is controlled by the value of termination resistance V
term
and the amount of line current I
O
(which is controlled by the current driver
29
). It is desirable to limit the line voltage swing as much as possible to enable higher bus speeds. If the voltage swing is too small, however, a receiving component will not be able to reliably distinguish between high and low logic level voltages.
FIG. 2
also illustrates how the line voltage is interpreted at receiving component or device
28
. Specifically, the received line voltage V
O
is compared to reference voltage VREF by a comparator
40
. If V
O
is greater than VREF, the line voltage represents a high logic level. If V
O
is less than VREF, the line voltage represents a low logic level.
For this determination to be valid, the transmitting component needs to set its V
OH
and V
OL
relative to VREF. Preferably, V
OH
and V
OL
are established symmetrically around VREF. In the example of
FIG. 3
, V
OH
is 2.5 volts, V
REF
is 2.2 volts, and V
OL
is 1.9 volts. This yields a 0.6 volt voltage swing: 0.3 volts on either side of VREF.
FIG. 3
shows a circuit for creating a symmetrical voltage swing around VREF during a calibration process. This circuit, which is used only during the calibration, utilizes two different bus lines
60
and
61
, each of which are similar to the bus line
26
shown in FIG.
2
.
The calibration circuit has current drivers
62
and
63
, and a current control
64
which in this case is an up/down counter. Current drivers
62
and
63
are switched on and off by data control lines (not shown) to create high and low voltage levels V
OH
and V
OL
on the corresponding bus lines. When a driver is on, the magnitude of its output current is determined by the value contained in up/down counter
64
.
Bus lines
60
and
61
extend to receiving components and a termination resistor (not shown). Within the transmitting component, however, the high and low output voltages V
OH
and V
OL
are sampled for purposes of adjusting the current driver outputs to create a symmetric voltage swing. Specifically, a simple R over R resistive voltage divider
66
is placed between a line producing a high logic voltage V
OH
and another line producing a low logic level V
OL
. In this case, it is assumed that line
60
is at the high voltage level, with current driver
62
inactive; and bus line
61
is at the low voltage level, with current driver
63
being active. Furthermore, the resistive divider
66
is configured to produce an intermediate output voltage V
I
that is equal to (V
OH
+V
OL
)/
2
. For symmetry around VREF, V
I
should be equal to VREF. A feedback system is used to minimize the voltage difference between V
I
and VREF. Both V
I
and VREF are connected to the inputs of a comparator
68
, which produces a logic voltage V
F
that is high when V
I
−VREF>0, and low when V
I
−VREF<0. V
F
is then connected to counter
64
. The output of the counter, in turn, is connected to control the output of current drivers
62
and
63
.
The circuit works as follows. During calibration, counter
64
is enabled and/or clocked, and repetitively adjusts its output either up or down depending on the logic value of V
F
. This increases or decreases the output of current driver
63
. The output current is thus adjusted until the value of counter
64
has settled. At this point, V
I
−VREF=zero—meaning that V
I
=VREF and that V
OH
and V
OL
are symmetric around VREF. At this point, the value of counter
64
is frozen until the next calibration (although minor adjustments might be made by temperature control circuits).
In most cases, this calibration is performed at system initialization. Optionally, the calibrated current control value (from the counter) can be stored in a current control register and used during normal bus operation to control the magnitude of I
O
. This value can then be subject to temperature correction circuits to determine the current control value at any given time. Alternatively, the calibration can be performed periodically to account for temperature and voltage variations.
Ideally, both the transmitting component and a receiving component have the same value of VREF. In practice, however, this can be difficult to achieve due to signal line losses and/or noise. Accordingly, VREF at the receiving component is often somewhat different than VREF at the transmitting component. Furthermore, V
OH
and V
OL
often change as they propagate through the signal line, again due to losses and noise. Thus, the relationship between V
OH
, V
OL
and VREF may not be the same at the transmitting component as it is at the receiving component. In other words, V
swing
might not be symmetric around VREF by the time the signals reach a receiving component.
In the bus configuration described above, line losses generally affect V
OL
more than V
OH
. At V
OL
, the voltage is being produced by a current through the bus line, so the voltage can be affected along the length of the bus line by resistive and capacitive loads. At V
OH
, however, there is no line current, and therefore less opportunity for the voltage to be affected along the length of the bus line. This situation affects both the line voltage swing and the relationship of V
OL
with VREF.
The non-symmetry at the receiving component has negative effects. If V
OL
11
is higher at the receiving component, the voltage margin from VREF to V
OL
is decreased. When V
OL
is lower at the receiving component, low-side margin is increased, but the higher V
swing
would cause more reflections, w

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