Optics: measuring and testing – Inspection of flaws or impurities – Surface condition
Reexamination Certificate
2001-06-27
2003-04-08
Whitehead, Jr., Carl (Department: 2813)
Optics: measuring and testing
Inspection of flaws or impurities
Surface condition
Reexamination Certificate
active
06545753
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to a system and method for monitoring and regulating dual damascene processing of a semiconductor substrate. In particular, the present invention relates to regulating dual damascene methods of forming trenches, holes and interconnects using a dual damascene process.
BACKGROUND
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there have been, and continue to be, efforts toward scaling down device dimensions (e.g., at sub-micron levels) on semiconductor wafers. In order to accomplish such high device packing densities, smaller and smaller feature sizes are required. This may include the width and geometry of vias between layers, the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry, such as corners and edges, of various features. The dimensions of and between such small features can be referred to as critical dimensions (CDs). Reducing CDs, and reproducing more accurate CDs facilitates achieving higher device densities.
The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips), typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit may be formed on a single wafer. Each step can affect the CDs of the ICs. Generally, the manufacturing process involves creating several patterned layers on and into the substrate that ultimately forms the complete integrated circuit. This layering process creates electrically active regions in and on the semiconductor wafer surface. One of the steps employed in manufacturing a semiconductor is an etch step, where selected portions of a layer (e.g., unprotected oxide layer) are removed from a wafer. Such an etch step may comprise a multi-step process that may be performed many times during the fabrication of a semiconductor. Thus, the size, shape and isolation of the electrically active regions, and thus the reliability and performance of integrated circuits employing such regions depend, at least in part, on the precision with which etching can be performed. One particular etching process is known as a dual damascene process. Conventionally, such dual damascene processes have relied on etch-stop layers and/or reproducing etch times to facilitate achieving desired etch depths for vias and/or trenches. But such conventional techniques suffer from drawbacks (e.g., additional layer, inexact/indirect control).
Conventional semiconductor devices typically comprise a semiconductor substrate, normally made of monocrystalline silicon, and a plurality of dielectric and conductive layers formed thereon. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Such interconnection lines, made of metal interconnect materials, generally constitute a limiting factor in terms of size (width) and various functional characteristics of the integrated circuit. As such, there exists a need to provide a reliable interconnection structure having a small size yet capable of achieving higher operating speeds, improved signal-to-noise ratio and improved reliability.
Using a dual damascene process, semiconductor devices are patterned with several thousand openings for conductive lines and vias which are filled with a conductive metal, such as aluminum or copper, and serve to interconnect the active and/or passive elements of the integrated circuit. The dual damascene process also is used for forming the multilevel signal lines of conductive metal in the insulating layers of multilayer substrate on which semiconductor devices are mounted.
Due to the extremely fine patterns that are exposed on the photo resist, controlling the dual damascene process, whereby oxide and/or other conductive or insulating layers are removed, is a significant factor in achieving desired critical dimensions. Achieving greater precision in dual damascene processes can result, for example, in achieving more precise CDs (e.g., desired via depths). Thus, a system and/or method to control dual damascene processes is desired.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides a system and method for monitoring and/or controlling dual damascene methods so that an etch-stop layer is not required and so that more precise control than is possible via timed etch processes is achieved. An exemplary system can employ one or more light sources arranged to project light onto one or more features and/or gratings on a wafer, and one or more light sensing devices (e.g., photo detector, photodiode) for detecting light reflected and/or refracted by the one or more features (e.g., trenches, vias) and/or gratings as the features and/or gratings are being processed by a dual damascene method. A grating is usually divided into a large number of sufficiently thin planar grating slabs to approximate an arbitrary profile. During dual damascene processing, the light reflected from the one or more features and/or gratings is indicative of at least one parameter of the dual damascene process (e.g., depth of etch, percent completion of etching) that can be measured to determine whether desired depths, diameters, profiles, critical dimensions (CDs), and so on are being achieved and to determine whether adaptations to the dual damascene process should be undertaken.
One or more etching components can be arranged to correspond to a particular wafer portion. Alternatively, one or more etching components can be employed to etch various wafer portions. The etching components may be, for example, a gas plasma apparatus employed in reactive ion etching. It is to be appreciated that any suitable etching components may be employed with the present invention. The etching components are selectively driven by the system to etch away oxide and/or other materials (e.g., in a polysilicon) at a desired location, at a desired rate, to a desired depth and/or to a desired width. The etching process is monitored by the system by comparing the etch results (e.g., CDs, depth, height, profiles) on the features and/or gratings on the wafer to desired results. Data gathered during such monitoring can be employed to determine whether an etch process employed in a dual damascene method is complete, and thus, to control the end point of such a dual damascene etch process. As a result, more optimal etching process characterization is achieved, which can reduce the time and expense of producing an etch process that can subsequently be employed to produce high quality integrated circuits. Additionally, and/or alternatively, data concerning etch process conditions that resulted in favorable and/or unfavorable CDs can be stored to facilitate reproducing favorable etch process conditions for subsequent portions of the wafer being etched and/or for subsequent wafers. In one example of the present invention, the data that is gathered is analyzed using machine learning techniques to facilitate more quickly and more accurately adapting the etch process being characterized and to facilitate more quickly and more accurately adapting subsequent etch processes.
One aspect of the present invention provides a system for monitoring and controlling an etch process associated with a dual damascene process. The system includes an etching component operative to etch a portion of a wafer and an etch component driving system operably connected to the
Singh Bhanwar
Subramanian Ramkumar
Templeton Michael K.
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Jr. Carl Whitehead
Thompson Craig
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