Bus interfacing circuit for a FIFO memory

Details Bus interfacing circuit for a FIFO memory Bus interfacing circuit for a FIFO memory

1994-10-27

1995-10-17

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

36518905, 365240, 326 90, H03K 190175, G11C 700

Patent

active

054594138

ABSTRACT:
A bus interfacing circuit for permitting a unilateral read/write first-in first-out memory to perform first-in first-out functions without data bumping when operated in bilateral data buses is disclosed. The bus interfacing circuit includes a first OR-logic gate for operating upon a host write signal and a peripheral write signal applied thereto, a second OR logic gate for operating upon a host read signal and a peripheral read signal applied thereto, a first-in first-out memory cell for accessing data in response to output signals from the first and second OR logic gates, a data propagation director for generating a first direction signal and a second direction signal in accordance with a generation order between the host and peripheral write signals, a first data switch for transferring data fed in a host data input terminal to said first-in first-out memory cell in response to said first direction signal, a second data switch for transferring data applied from the first-in first-out memory cell to a data bus in response to the host read signal, and a third data switch for transferring data loaded on the data bus to the first-in first-out memory cell.

REFERENCES:
patent: 4315167 (1982-02-01), Pelc
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patent: 4873667 (1989-10-01), Geadah et al.
patent: 5056005 (1991-10-01), Kaneko et al.
patent: 5151615 (1992-09-01), Egawa
patent: 5195055 (1993-03-01), Mizuoka et al.
patent: 5200925 (1993-04-01), Morooka
patent: 5248908 (1993-09-01), Kimura
patent: 5396460 (1995-03-01), Harada et al.

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