Bus interface unit having selectively enabled buffers

Details Bus interface unit having selectively enabled buffers Bus interface unit having selectively enabled buffers

1997-10-20

2000-06-20

Thai, Xuan M.

Electrical computers and digital processing systems: support

Computer power control

Power conservation

713600, G06F 132

Patent

active

060790245

ABSTRACT:
A computer system includes a bus interface with a plurality of data buffers. Each data buffer is clocked by an individual clock signal. To reduce the power consumption of the bus interface unit, the clock signals of the data buffers that are inactive are disabled during the period of inactivity. The bus interface unit includes a clock control unit that monitors a data bus coupled to the bus interface to determine when a bus cycle begins and the type of bus cycle. The clock control unit additionally monitors memory and CPU buffer signals that indicate which, if any, buffers are being accessed by the memory or CPU. From this information, the clock control unit determines which buffers are active and inactive, and outputs control signals to a clock unit to disable the clock signals associated with inactive buffers.

REFERENCES:
patent: 5603037 (1997-02-01), Aybay
patent: 5615376 (1997-03-01), Ranganathan
patent: 5721839 (1998-02-01), Callison et al.

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