Bus interface unit having dual purpose transaction buffer

Details Bus interface unit having dual purpose transaction buffer Bus interface unit having dual purpose transaction buffer

1998-08-25

2000-08-08

Auve, Glenn A.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710130, 710131, G06F 1342

Patent

active

061015687

ABSTRACT:
A bus interface unit includes a random-access transaction buffer and at least one pointer queue. The transaction buffer stores entries for both in-order transactions and combinable write transactions, and the pointer queue stores pointers to the buffer entries for in-order transactions so as to order the in-order transactions. When a received combinable write transaction has a writing address that falls within the address range of a stored combinable write transactions, the received transaction is merged with the stored transaction. Additionally, a method is provided for processing requested bus transactions. The bus interface unit determines if a requested transaction is a combinable write transaction. If not, address and data information for the requested transaction is loaded into an empty entry in a random-access buffer, and a pointer to that buffer entry is placed in a pointer queue. Alternatively, if the requested transaction is a combinable write transaction, the bus interface unit determines if the transaction's write address falls within the address range of a stored combinable write transaction. If so, the requested transaction is merged with the stored transaction. In a preferred embodiment, if the write address does not fall within the address range of any stored combinable write transaction, the data information for the requested transaction is loaded into an empty entry in the random-access buffer.

REFERENCES:
patent: 5185869 (1993-02-01), Suzuki
patent: 5526495 (1996-06-01), Shibata et al.
patent: 5737566 (1998-04-01), Sparks et al.
patent: 5778431 (1998-07-01), Rahman et al.

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