Bus interface timing adjustment device, method and...

Details Bus interface timing adjustment device, method and... Bus interface timing adjustment device, method and...

2005-04-05

2005-04-05

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S502000, C710S058000, C710S305000, C714S043000

Reexamination Certificate

active

06877103

ABSTRACT:
A timing adjustment device, method and chip for a bus interface. Through repetitive adjustment of the amount of phase shift in the clocking signal to the bus interface, read/write testing of the bus interface and checking for the correctness of the read/write data, suitability of the phase shift in the memory bus clocking signal for operating normally is determined. Hence, a safety range for the amount of phase shift in the bus interface timing signal is found and the phase shift of the bus interface timing signal is set to the mid-point of the safety range. The method may also be applied to a system bus and the timing adjustment of signals between a control chipset bus and a memory bus.

REFERENCES:
patent: 5159291 (1992-10-01), Ghoshal
patent: 5757381 (1998-05-01), Shoji et al.
patent: 5978926 (1999-11-01), Ries et al.
patent: 6502212 (2002-12-01), Coyle et al.

Affiliated with

Also associated with

Rating

Bus interface timing adjustment device, method and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bus interface timing adjustment device, method and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bus interface timing adjustment device, method and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3418485