Bus interface for transfer of SONET/SDH data

Details Bus interface for transfer of SONET/SDH data Bus interface for transfer of SONET/SDH data

2001-05-03

2004-11-16

Thai, Xuan M. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C370S465000, C370S389000

Reexamination Certificate

active

06820159

ABSTRACT:

FIELD
This invention relates generally to a bus interface used to transfer SONET/SDH data. More specifically, this invention relates to a bus interface for the transfer of SONET/SDH data over a serial backplane.
BACKGROUND OF THE INVENTION
In conventional data communication systems, a local node with a large number of SONET/SDH terminations, may process a large variety of payload types. Common payloads are Asynchronous Transfer Mode (ATM), Packet Over SONET (POS), and Time Division Multiplexing (TDM) traffic. In general, each of the payload types is processed by specialised hardware residing in disparate cards. For traffic not terminating in the local node, the traffic may be groomed and transported from input fibers to arbitrary output fibers.
The Combus standard provides a common interface between SONET termination devices and payload processing devices. However, the Combus standard is limited to OC-3 streams and contains 11 signals per interface. For a high capacity node, the number of signals required typically exceeds the limits of the Combus standard.
Another existing approach to connecting SONET/SDH termination devices to payload processing devices requires the reconstruction of a serial SONET/SDH stream post SONET/SDH termination. However, this method suffers from the disadvantage of requiring duplicate SONET/SDH processing at the payload processing devices. Another disadvantage of this method is the lack of guaranteed transitions on the serial links as SONET/SDH scrambling only provides a statistical amount of transitions. As a result, complex clock and data recovery phase-locked loops are often required.
To overcome the lack of guaranteed transitions on the serial links, an alternative approach is used that involves reconstructing a serial SONET/SDH stream post SONET/SDH termination and then applying a line code that guarantees transitions on the serial link. Again, this method suffers from the disadvantage of requiring duplicate SONET/SDH processing at the payload processors.
It is, therefore, an object of this invention to provide an improved bus interface to connect SONET/SDH termination devices with payload processing devices.
It is a further object of this invention to provide a bus interface to connect SONET/SDH termination devices with payload processing devices utilizing a minimum number of signals.
It is still a further object of this invention to provide a bus interface that can scale with future advances in bandwidth in serial link technology.
SUMMARY OF THE INVENTION
These and other objects of the invention are provided in a new and improved method of connecting SONET/SDH termination devices with payload processing devices while requiring a minimum number of signals. The protocol used in the method allows the SONET/SDH termination device to handoff at the SONET line termination level, path termination level, and tributary termination level (SDH multiplex section termination level, high-order path terminating level and low-order path terminating level). The protocol is also capable of scaling with future advances in bandwidth in serial link technology.
The method consists of providing a transmit interface and a receive interface. In operation, the transmit interface receives an incoming SONET/SDH signal stream and converts the SONET/SDH signal stream into outgoing low voltage differential signal (LVDS) levels. The SONET/SDH signal streams are mapped into
8
B/
10
B control characters to label the SONET/SDH frame boundaries. Potential SONET/SDH frame boundaries include transport frame, high-order path frame and low-order path frame boundaries.
The receive interface receives incoming LVDS signal levels and converts the LVDS levels into outgoing SONET/SDH signal streams. The
8
B/
10
B control characters labeling the SONET/SDH frame boundaries are decoded into SONET/SDH control signals.
By mapping a descrambled SONET/SDH data stream into
8
B/
10
B control characters, proper data transitions on serial links can be ensured. Also, the mapping preserves the DC balance.
Preferably, the
8
B/
10
B control characters that have an even number of ones and zeros have their positive and negative disparity codes treated as separate control characters. Line code violations of these
8
B/
10
B characters may be used to monitor error performance of serial links.
Alternatively, the signals may be stored in a buffer. The signals can then be transferred using a universal frame pulse with a software programmable delay to allow the transfer of a single SONET/SDH signal over multiple links.
Preferably, the method also includes providing transparent in-band error reporting such that errors detected at a SONET/SDH receiver can be transferred to a transmitter to construct remote error and defect indication codes. The method may also include inserting a pseudo-random bit sequence pattern in serial transmit links to allow data path verification prior to injection of an actual payload.
Alternatively, the method may include overwriting one of the E
1
and B
1
bytes to form a pattern. This pattern allows in-service monitoring of link functionality as well as monitoring of downstream cross-connect mis-configurations. Optionally, the bytes in E
1
may be overwritten with the complement of a value in B
1
bytes.
The invention also includes a bus interface device operative to perform the steps of the method described above.
Other objects and advantages of the invention will become clear from the following detailed description of the preferred embodiment, which is presented by way of illustration only and without limiting the scope of the invention to the details thereof.


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ITU G.707 (03/96) from International Telecommunication Union Series G: Transmission Systems and Media Network node interface for the synchronous digital hierarchy (SDH).
A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code from IBM Journal of Research & Development, Sep., 1983. Author A.X. Widmer and P.A. Franaszek.
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