Bus interface for I/O device with memory

Details Bus interface for I/O device with memory Bus interface for I/O device with memory

2001-03-13

2004-03-23

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

C326S041000, C326S047000

Reexamination Certificate

active

06710620

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the field of computer systems and, in particular, to the transfer of data to and from a memory of an input/output device by a central processing unit.
BACKGROUND
When transferring data between a processor and an input/output (I/O) device having its own memory such as an independent direct memory access (IDMA) device special software drivers and software are required. A special software driver is required when connecting the I/O device to the processor's communication bus. In addition software is required to communicate with the I/O device. Writing to an area in an I/O device is not achieved using a simple memory mapped access. A function call is required with the destination address and the data as the parameters. A read is handled similarly with a function call with the source address as a parameter. Each function call adds a request, parameter pushing and return instructions to every read and/or write operation. Every time the processor communicates with the I/O device to perform a read or write operation a function call is invoked. When a series of read/writes are required the process becomes cumbersome.
Another difficulty in communicating data to an I/O device having its own memory is when multiple processes are running simultaneously. For example, when there is contention between processes, data may be written to the wrong address because there is no arbitration between the function calls. System developers have difficulty simulating and debugging systems containing I/O devices having their own memory and these types of errors may go undetected. Simulating and debugging are more difficult than with standard memory devices because the software to support the function calls associated with communicating with the I/O device are not always well documented. The process of determining what steps, e.g., function calls were taken to communicate with the I/O device and write appropriate code to get the data in the correct place is time consuming.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improvements in bus interfaces for I/O devices having their own memory in CPU systems.
SUMMARY
The above mentioned problems with the transfer of data between an I/O device and a CPU and other problems are addressed by embodiments of the present invention and will be understood by reading and studying the following specification.
In one embodiment, an electronic system is provided. The electronic system includes a logic device and at least one input/output interface coupled to the logic device. The electronic system further includes an input/output (I/O) device with memory coupled to the at least one input/output interface, wherein the memory of the I/O device is mapped as an address space region that is directly readable and writable by a processor.
In another embodiment, an electronic system is provided. The electronic system includes a communication bus, a processor coupled to the communication bus and at least one memory device coupled to the communication bus. The electronic system further includes a logic device coupled to the communication bus and at least input/output interface coupled to the logic device. In addition, the electronic system includes an input/output (I/O) device with memory coupled to the at least one input/output interface. The memory of the I/O device is mapped as a single address space region and the at least one memory device and the memory of the I/O device are directly readable and writable by the processor.
In a further embodiment, a method of writing data to memory of a peripheral device coupled to a communication bus is provided. The memory is mapped as an address space region and the address space is writable and readable by a processor associated with the communication bus. The method includes monitoring the communication bus and decoding an address signal on the communication bus. When the address signal is associated with the memory of the peripheral device, generating at least one control signal. The method further includes providing the control signal to an input/output interface associated with the peripheral device and writing to the memory of the peripheral device.


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