Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-10-11
2003-10-21
Vo, Tim (Department: 2189)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S308000, C710S310000, C711S146000, C711S202000, C711S205000, C711S206000, C711S207000, C711S208000, C711S209000, C714S006130, C714S006130, C714S718000, C714S719000
Reexamination Certificate
active
06636925
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bus interface preparation apparatus for preparing a bus interface circuit provided between a central processing unit which constitutes a master and hardware which constitutes slaves for the central processing unit.
2. Background Art
Conventionally, when designing a bus interface circuit between the central processing unit (hereinafter, called CPU)
400
as a master and a hardware (hereinafter, called HW)
1
and HW
2
as slaves for the master, as shown in
FIG. 25
, addresses (hereinafter, called global addresses) to be read and written from CPU to memories and to registers are arranged based on the text form
410
or a table form
411
, shown in FIG.
26
. In addition, based on the text form
410
or the table form
411
, the designer describes the interface circuit by hardware description language and the like. It is noted that the bus interface circuit is constituted by address decoders as a whole provided for respective memories and registers provided between the CPU as the master, and hardware as slaves for the master, and each address decoder comprises an enable signal generating circuit and an address conversion circuit.
However, since the addresses have been arranged in text form or in table form, when it is necessary to add a new register or new memory, when modifying the address of the described register, or when it is necessary to modify the top address of a memory, or the memory size, it is necessary to confirm whether there is a overlapping portion in the registers or the memories for correcting the addresses every time.
Such modifications of the addresses may be carried out for several times depending on the designer's will, and are troublesome and may cause errors, and thus imposes a burden on the designer of the apparatus.
Furthermore, for the registers and memories for reading and writing from the CPU, a variety of cases are encountered such as the usage of a different addresses for reading and writing, and the case that the data are divided into a plurality of bits for allocating these bits to different addresses. In such a complicated address designation, description errors are liable to occur and the description operations become complicated.
Therefore, it is required to provide a tool, capable of preventing duplication of the addresses, treating complicated address designations, and automatically generating a bus interface circuit from the address map.
SUMMARY OF THE INVENTION
It is therefore, an object of the present invention to provide a bus interface circuit preparation apparatus, capable of preventing duplication of addresses in the registers and memories of the bus interface circuit and also capable of facilitating the visual confirmation of the address arrangement on an image screen such as a display.
Another object of the present invention is to provide a bus interface preparation apparatus capable of automatically preparing a simplified bus interface circuit even when a complicated addresses are designated.
Another object of the present invention is to provide a bus interface circuit preparation apparatus, capable of warning the user about the duplication of the addresses and the generation of hardware that is not preferable for the area if the display.
According to its first aspect, the present invention provides a bus interface circuit preparation apparatus, which outputs a hardware description language expressing said bus interface circuit by inputting a bus interface description including a memory element, which is disposed between the central processing unit constituting a master and hardware constituting a slave for said central processing unit, comprising: an extracting portion for extracting data related to the address of said memory element; a bit data memory portion for storing the address allocated to said memory element based on the data extracted by said extracting portion; and an address competition detecting portion for detecting duplication of the address in the memory element based on the data extracted by said extracting portion, and the address information stored in said bit data memory portion.
According to the second aspect, the bus interface circuit preparation apparatus, which outputs a hardware description language expressing said bus interface circuit by inputting a bus interface description including a memory element, which is disposed between the central processing unit constituting a master and hardware constituting a slave for said central processing unit, comprises: an RW address comparison portion for determining whether the reading global address and the writing global address, both allocated to the same memory element, are identical, based on the inputting bus interface description; a determination portion for determining whether said reading global address and said writing global address are divided to form different addresses in the bit unit; and a select signal generating circuit for outputting a select signal which becomes active when said global address is assigned, providing that said reading global address and said writing global address are identical and that said global addresses are different addresses in the bit unit, and a circuit generating potion for generating conversion circuits corresponding to each of said global addresses for converting said global addresses to local addresses of said memory element.
According to the third aspect, the bus interface circuit preparation apparatus, which outputs a hardware description language expressing said bus interface circuit by inputting a bus interface description including a memory element, which is disposed between the central processing unit constituting a master, and hardware constituting a slave for said central processing unit, comprises: an RW address comparison portion for determining whether or not the reading address and the writing address, both allocated to the same memory element, are identical; a determination portion for determining whether said reading global address and said writing global address are divided to form different addresses in the bit unit; a select signal generating circuit for outputting the select signal which becomes active when said global address is assigned, providing that said reading global address and said writing global address are different addresses and that respective addresses of said reading global address are identical to said writing global address, and a circuit generating potion for generating conversion circuits corresponding to said writing global address and said writing global address for converting said global addresses to local addresses of said memory element.
According to the fourth aspect, the bus interface circuit preparation apparatus, which outputs a hardware description language expressing said bus interface circuit by inputting a bus interface description including a memory element, which is disposed between the central processing unit constituting a master and a hardware constituting a slave for said central processing unit, comprises: a RW address comparison portion for determining whether the reading address and the writing address, both allocated to the same memory element, are identical; a determination portion for determining whether said reading global address and the writing global address are divided to form different addresses in the bit unit; and a select signal generating circuit for outputting the select signal which becomes active when any one of said reading global address and said writing global address, which forms different addresses in the bit unit, is assigned, providing that said reading global address and said writing global address are different addresses and that at least any one of said reading global address and said writing global address forms different addresses in the bit unit, and a circuit generating potion for generating conversion circuits corresponding to each of said reading global address and to each of said writing global addresses for converting said global address
Maruyama Yuichi
Otsubo Motohide
Wakabayashi Kazutoshi
Foley & Lardner
NEC Electronics Corporation
Vo Tim
LandOfFree
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