Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-02-01
2002-02-05
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C710S120000, C710S053000
Reexamination Certificate
active
06345332
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bus interchange apparatus and a dual system.
Information processing systems and control systems employ a dual system to improve the reliability thereof. The dual system includes a bus interchange apparatus to connect system buses to each other. There is a requirement to smoothly transfer data between the system buses through the bus interchange apparatus.
2. Description of the Related Art
In a dual system of the prior art, fault information held by a register of any one of the bus interchange apparatuses is accessible only through one buffer thereof. If a buffer has no free space, an access request for the register from a bus controller is not written into the buffer, and therefore, the bus controller is unable to access the register. If an access request for the register is written into the buffer and if data to be transferred is not read out of the buffer due to a fault on the cross bus side, there will be no way to access the register. If the buffer has no free space or if the contents of the buffer cannot be read, the bus controller is unable to access the register.
If the register is inaccessible, fault information and repair information will not be written into and read out of the register. It is impossible for the prior art to locate a fault or carry out a reset operation to deal with the fault. As a result, the prior art must reset and restart the system as a whole by suspending services provided by the system.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a bus interchange apparatus and a dual system capable of accessing a register that holds fault information, etc., without regard to the conditions of buffers.
In order to accomplish the objects, the present invention provides a bus interchange apparatus for connecting first and second system buses to each other through a cross bus to interchange information between the first and second system buses. The apparatus has a first bus controller connected to the system bus, a second bus controller connected to the cross bus, buffers arranged between and connected to the first and second bus controllers, for relaying information between the first and second bus controllers, and a register to which fault information, etc., is written. The register is directly accessible from the first and second bus controllers.
The first and second bus controllers have reception controllers for writing information, which is to be transferred from a sender to a receiver, into the buffers if the buffers are not full, and if the buffers are full, sending a busy signal to the sender without writing the information into the buffers, and transmission controllers for reading the information out of the buffers and transmitting the same to the receiver. The reception controllers are able to write fault information, etc., into the register in response to an access request for the register irrespective of whether or not the buffers are full. The transmission controllers are able to read fault information, etc., out of the register in response to an access request for the register and send out the read information irrespective of whether or not the buffers are full.
The transmission controllers may have each a counter for counting the number of retry operations that are carried out when information read out of the buffer and transmitted to a receiver is not normally received by the receiver, and a unit for writing a retry-over signal into the register if the number of retry operations exceeds a retry limit.
The transmission controllers may have each a limit register for storing the retry limit and a coincidence unit for comparing the number of retry operations counted by the counter with the retry limit, and if they agree with each other, providing the retry-over signal.
The transmission controllers may have each a sender ID unit for identifying a sender, a counter provided for each sender to be identified by the sender ID unit, for counting the number of retry operations carried out for the sender, a limit register provided for each counter, for storing a retry limit for the counter, and a coincidence unit provided for each counter, for comparing the number of retry operations counted by the counter with the corresponding retry limit, and if they agree with each other, providing a retry-over signal.
The reception controllers may have each a unit for determining whether or not an access is to the register and a unit for writing information into the buffer if the access is not to the register and if the buffer is not full, and writing the information into the register irrespective of whether or not the buffer is full if the access is to the register.
The present invention also provides a dual system having first and second system buses that are connected to processors, respectively. The dual system employs bus interchange apparatuses having a cross bus for connecting the system buses to each other. Each of the bus interchange apparatuses has a first bus controller connected to one of the first and second system buses, a second bus controller connected to the cross bus, buffers arranged between and connected to the first and second bus controllers, for relaying information between the first and second bus controllers, and a register to which fault information, etc., is written and which is accessible directly from the first and second bus controllers. One of the system buses serving as a sender refers to the register to see if there is a fault in a location to which the bus interchange apparatus is connected, if the sender receives no response or an error response from the bus interchange apparatus to a request for transferring data from the sender to the other system bus serving as a receiver.
Alternatively, the sender may tray again to transfer the data to the receiver, if the register holds a retry-over signal and indicates no fault in the location to which the bus interchange apparatus is connected.
Alternatively, the sender may terminate the data transfer to the receiver, if the register holds a retry-over signal and indicates a fault in the receiver.
The bus interchange apparatuses of the dual system may each have any structure mentioned above.
REFERENCES:
patent: 5345559 (1994-09-01), Okazaki et al.
patent: 5526495 (1996-06-01), Shibata et al.
patent: 5933613 (1999-08-01), Tanaka et al.
patent: 56-52990 (1981-05-01), None
patent: 9-73429 (1997-03-01), None
patent: 63-86054 (1998-04-01), None
Dharia Rupal
Fujitsu Limited
Rosenman & Colin LLP
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