Bus hold circuit with overvoltage tolerance

Details Bus hold circuit with overvoltage tolerance Bus hold circuit with overvoltage tolerance

1999-06-01

2000-11-21

Nguyen, Viet Q.

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 80, 326 81, 326 30, 326 31, 326 33, 327333, H03K 190185

Patent

active

061508454

ABSTRACT:
A CMOS-based bus-hold circuit having overvoltage tolerance. The bus-hold circuit of the present invention includes, in addition to conventional input and latching inverters, a sense circuit and an arbiter circuit designed in combination to block overvoltage events from powering the latching inverter. The sense circuit includes a comparator designed to compare the potential of a standard high-potential power supply rail to the potential associated with a signal applied to the bus-hold circuit's input node. The higher of those two potentials is used to activate the arbiter circuit that in turn couples the higher of those two signals to a pseudo high-potential power rail. The pseudo high-potential power rail is used to supply power to the latching inverter such that the latching inverter will not be activated during overvoltage conditions, particularly when the circuit is in its high-impedance state. The bus-hold circuit may be similarly designed to establish an undervoltage tolerance as well.

REFERENCES:
patent: 5391061 (1995-02-01), Davis
patent: 5432462 (1995-07-01), Obregon et al.
patent: 5610537 (1997-03-01), Hastings
patent: 5646553 (1997-07-01), Mitchell et al.
patent: 5828233 (1998-10-01), Nguyen et al.
patent: 5914844 (1999-06-01), Lutley et al.
patent: 5983320 (1999-11-01), Farmwald et al.
patent: 6049242 (2000-04-01), Lutley et al.

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