Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2005-08-02
2005-08-02
Ray, Gopal C. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S306000, C710S316000
Reexamination Certificate
active
06925517
ABSTRACT:
A bus for supporting plural signal line configurations and the method to switch it, used to operate in a bus between the control chips to maintain its operation flexibility. When the data transfer load in between the control chips is suitable for the bi-direction transfer, the signal line configuration of the bi-direction transfer is selected. When the direction of the bi-direction transfer switches frequently, the other signal line configuration is selected. That is, the bus signal lines are divided into two parts, each part is in charge of the data transfer in each uni-direction to avoid the turn around cycle that impacts the transfer performance.
REFERENCES:
patent: 4635250 (1987-01-01), Georgiou
patent: 6545504 (2003-04-01), Sun et al.
patent: 6577161 (2003-06-01), Sun et al.
patent: 6678829 (2004-01-01), Teggatz et al.
patent: 6683876 (2004-01-01), Tornes et al.
“A subscriber line interface processor for asynchronous transfer mode switching system” by Yamamoto, K.; Kihara, K.; Yamazaki, K.; Kobayashi, H. (abstract only) Publication date: Feb. 14-16, 1990.
Kao Chih-kuo
Peng Sheng-Chang
Tsai Chau-Chad
Tsai Chi-Che
Jiang Chyun IP office
Ray Gopal C.
VIA Technologies Inc.
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