Bus for high frequency operation with backward compatibility...

Details Bus for high frequency operation with backward compatibility... Bus for high frequency operation with backward compatibility...

1998-07-15

2001-02-06

Lee, Thomas C. (Department: 2782)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output process timing

C710S060000, C710S108000, C713S501000

Reexamination Certificate

active

06185642

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to computer systems, specifically to a method and apparatus for interconnecting various computer components (i.e., peripheral devices), and more particularly to such a method and apparatus which allows backward compatibility with different computer bus designs, including bus designs having different clock speeds.
2. Description of Related Art
A typical structure for a conventional computer system includes one or more processing units connected to a system memory device (random access memory or RAM) and to various peripheral, or input/output (I/O), devices such as a display monitor, a keyboard, a graphical pointer (mouse), and a permanent storage device (hard disk). The system memory device is used by a processing unit in carrying out program instructions, and stores those instructions as well as data values that are fed to or generated by the programs. A processing unit communicates with the other components by various means, including one or more interconnects (buses), or direct access channels. A computer system may have many additional components, such as serial and parallel ports for connection to, e.g., printers, and network adapters. Other components might further be used in conjunction with the foregoing; for example, a display adapter might be used to control a video display monitor, a memory controller can be used to access the system memory, etc.
Several different bus designs have been developed for interconnecting the various computer components. The original personal computer (PCs) introduced by International Business Machines Corp. (IBM—assignee of the present invention) used an “expansion” bus referred to as the XT bus, which allowed a user to add various optional devices, such as additional memory (RAM), sound cards, telephone modems, etc. This early design was improved upon by adding more data and address lines, new interrupt lines, and direct memory-access (DMA) control lines, to create the well-known AT bus, which is also referred to as the Industry Standard Architecture (ISA) bus. The AT design allowed the microprocessor to run at a faster speed than the expansion bus. A 32-bit extension to this bus was later created, which is referred to as the Extended Industry Standard Architecture (EISA). Another 32-bit expansion bus developed by IBM is the Microchannel Architecture (MCA) bus.
In addition to the foregoing designs, several other bus designs have been developed allowing the use of a system bus which interconnects the processor and the system memory device(s), along with a separate, local bus which interconnects the peripheral devices to the system bus (using a bus bridge). Two well-known standards are the Video Electronics Standards Association (VL) bus, and the Peripheral Component Interconnect (PCI) bus.
The 33 MHz PCI specification allows up to 4 PCI-compliant expansion cards to be installed in “slots” constructed along the PCI bus. More specifically, 10 “loads” are allowed, with each slot (connector) and its corresponding card together comprising two loads (a soldered device is counted as one load). An expansion bus controller for a system's ISA, EISA, or MCA slots can optionally be installed as well, providing increased synchronization for all of the system's expansion bus-installed resources. A PCI host bridge provides synchronization between the system bus and the PCI bus, and allows certain “intelligent” PCI-compliant adapters to perform tasks concurrently with the microprocessor, using a technique called bus mastering.
A typical PCI system
10
is illustrated in FIG.
1
. System
10
includes a central processing unit (CPU)
12
, firmware or read-only memory (ROM)
14
, and a dynamic random access memory (DRAM)
16
which are all connected to a system bus
18
. CPU
12
, ROM
14
and DRAM
16
are also coupled to a PCI local bus
20
using a PCI host bridge
22
. PCI host bridge
22
provides a low latency path through which processor
12
may access PCI devices mapped anywhere within bus memory or I/O address spaces. PCI host bridge
22
also provides a high bandwidth path that allows the PCI devices to access DRAM
16
.
Attached to PCI local bus
20
are a local area network (LAN) adapter
24
, a small computer system interface (SCSI) adapter
26
, an expansion bus bridge
28
, an audio adapter
30
, and a graphics adapter
32
. Lan adapter
24
is used to connected computer system
10
to an external computer network
34
. SCSI adapter
26
is used to control high-speed SCSI disk drive
36
. Expansion bus bridge
28
is used to couple an ISA expansion bus
38
to PCI local bus
20
. As shown, several user input devices are connected to ISA bus
38
, including a keyboard
40
, a microphone
42
, and a graphical pointing device (mouse)
44
. Other devices may also be attached to ISA bus
38
, such as a CD-ROM drive
46
. Audio adapter
30
controls audio output to a speaker
48
, and graphics adapter
32
controls visual output to a display monitor
50
.
In earlier computer systems, all of the peripheral components had to be connected (inserted in the PCI or ISA slots) at the time that the computer was first turned on, in order to properly register (initialize) the devices with the computer's operating system. These devices are checked during the system's power-on self test (POST), which includes a set of routines stored in ROM
14
(also referred to as read-only storage, or ROS) that test the peripherals to see if they are properly connected and operating.
In the earlier systems, if a device were simply not present on the bus during the POST, then it would not be recognized when it was later attached (while the computer was still running). Instead, those systems were required to be “rebooted” in order to be able to communicate with and utilize the later-added devices. “Rebooting” refers to the restarting of a computer system by reloading its most basic program instructions, viz., the operating system. A system can be rebboted using the software itself (a warm boot) or by actuating the system's hardware, i.e., the reset or power buttons (a cold boot). After rebooting, the new device can be identified using various techniques.
More recent computer systems have the ability to recognize devices which are added while the computer is operating, that is, without having to reboot the system and without requiring manual configuration steps. One example is the “plug and play” specification, which allows a PC to configure itself automatically to work with peripherals. A user can “plug” in a peripheral and “play” it without manually configuring the system. Plug and play operation requires both ROM that supports the specification, and a special expansion card. While this approach allows the system to recognize a newly added device, it is still often necessary to reset the system in order to properly initialize the device with the operating system. A further improvement in this area is the “hot-plug” specification, wherein separate reset lines are provided for each peripheral device, such that a device can be initialized with the operating system without requiring the entire system to be rebooted (this ability of the device/system is referred to as “hot-pluggable”).
One problem that has arisen with this multitude of bus designs is backward compatibility, particularly for bus components operating at different speeds. The current PCI bus architecture defines 33 and 66 MHz capability. The “M66EN” pin on the bus is used to indicate whether operation is to be at 33 MHz or 66 MHz. This pin is tied to ground in the 33 MHz design, but connected to pull-up resistors in 66 MHz devices. Therefore, if any 33 MHz device is connected to the bus, the M66EN pin will be grounded even if 66 MHz devices are present, and so a 66 MHz PCI host bridge will know to operate the bus at the lower speed of 33 MHz. The M66EN pin provides only limited compatibility, however, in that it is confined to these two specific clock speeds, and also in that operation of the bus

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