Bus error handling in a computer system

Details Bus error handling in a computer system Bus error handling in a computer system

1998-06-30

2001-07-03

Iqbal, Nadeem (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S043000

Reexamination Certificate

active

06256753

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to computer systems with a processor which communicates with I/O devices via an I/O bus, and to a monitor unit and method for such systems.
In such a system, bus cycles to I/O devices usually end with successful data transfer. If something goes wrong, the I/O cycles can end with a data exception. Data exception handling is a well known and accepted technique in computer system design. However, there are times when it is inconvenient or impossible to handle such a data exception in the software being executed in the processor.
An aim of the invention is to seek to avoid the need for data exception handling by the processor software.
SUMMARY OF THE INVENTION
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims.
In accordance with a first aspect of the invention, there is provided an I/O monitor for a computer system. The monitor comprises an interface mechanism for connection between a processor and an I/O bus and an error signal modifier configured to be operable to respond to an error signal from the I/O bus to substitute a determined response for passing to the processor.
By returning a determined response to the processor, as opposed to the bus error signal, the need for bus error exception processing by the processor software is removed. The determined response can be processed as appropriate without the need for exception processing.
Preferably, the monitor is operable to determine a resource forming the source of the bus error and to label the resource as defective. This can be achieved by maintaining a status register for the resource in the monitor.
The monitor can be operable to generate an interrupt when a resource is first labelled as defective.
Subsequently, further access to the resource by the processor will be handled by the monitor. The monitor can be arranged to respond to an I/O read operation to a resource labelled as defective to prevent the I/O read operation from being passed to the bus and to return a determined data response. It can be arranged to respond to an I/O write operation to a resource labelled as defective to discard the I/O write operation and to terminate with an acknowledgement as the determined response.
In accordance with another aspect of the invention, there is provided an I/O monitor for a computer system which includes an interface for connection between a processor and an I/O bus a mechanism for labelling a fault status of a resource connected to the I/O bus and an error signal mechanism for responding to an I/O operation from a processor addressed to a resource labelled as defective to provide a determined response to the processor. The determined response can be a determined data response for an I/O read operation and an acknowledgement for an I/O write operation.
In accordance with a further aspect of the invention, there is provided a computer system comprising at least one processing set and a monitor as described above.
The system can include a plurality of processing sets. The systems could be synchronously operating. Alternatively, at least one of the plurality of processing sets could be operable asynchronously of another one. The processing sets could each comprises a single processor, or multiple processors. For example, a processing set may be formed by a symmetric multiprocessor. The resource can be an I/O device.
The system can be a fault tolerant computer system. The monitor can include a voter determining equivalent operating of the processing sets by comparing I/O operations from the processing sets with the voter being located between the plurality of processing sets and the error signal modifier.
In accordance with yet a further aspect of the invention there is provided a method of reporting bus errors in a computer system comprising a processor and an I/O bus and a monitor between the I/O bus and the processor The method comprises steps of:
the monitor converting an error signal from an I/O bus into a determined response; and
the monitor passing the determined response to the processor.
In another aspect, the invention provided a method for handling I/O operations in a computer system comprising at least one processor, an I/O bus and a monitor located between the at least one processor and the I/O bus. The method comprises steps of:
the monitor maintaining a fault status for resources connected to the I/O bus; and
the monitor responding to an I/O operation from the processor addressed to a resource labelled as defective to provide a determined response to the processor.


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