Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
2001-02-09
2004-03-30
Dang, Khanh (Department: 2181)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C710S011000, C710S064000, C710S105000, C709S241000
Reexamination Certificate
active
06715010
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bus emulation apparatus for transferring data between peripheral circuits via a hub circuit.
2. Description of the Related Art
A hub or a network having a hub is described in the Japanese Unexamined Patent Publication Nos. 11-284636, No.11-168493, 11-88397, 62-220047 and 7-297853.
For example, Japanese Unexamined Patent Publication No. 11-284636 discloses a hub apparatus and a USB (Universal Serial Bus) communication system. This publication discloses an addition of a function of directly connecting data paths between devices to the hub apparatus.
Japanese Unexamined Patent Publication No. 11-88397 discloses a switching hub. In this publication, a serial/parallel converter is provided among a plurality of high speed network interface portions and a plurality of low speed network switching portions, the data transfer is performed in a serial data within the high speed network interface portion and in a parallel data within the low speed switching portion, and the data transfer rate can be switched.
The Japanese Unexamined Patent Publication No. 7-297853 discloses the polling of a remote station in an extensible round-robin local area network.
In a cabinet of a personal computer and a digital home-use electricity apparatus of the related art, a multi-drop connection mode used a parallel wired bus is generally used.
In such the connection mode of the related art, since the flattening and terminating of an impedance of the wiring path is difficult, it is difficult to raise a data transfer rate per one signal line. Therefore, the number of the wires increases and it suffers from the disadvantages of an increase of a wiring area, an increase of an electro magnetic interference (EMI), a limit of a wiring length, etc.
Furthermore, in a bus wiring and bus architecture of a large-scale integrated circuit (LSI) or a print circuit board of the related art, when transferring a digital signal such as an audio, a video, etc. between peripheral circuits, it is difficult to transfer other signal between other peripheral circuits at a same time.
Therefore, a bus emulation apparatus for satisfying functions of a parallel bus wiring, bus driver, bus receiver, etc. of the related art and overcoming the disadvantages in the existing bus as explained above has been demanded.
Note that serial network standards, such as the IEEE (Institute of Electrical and Electronics Engineers) 1394, Universal Serial Bus (USB) and Eithernet, are basically a Time-Division Multiple Access (TDMA) system, so it is difficult to perform a simultaneous multiple transfers in the same way as in a normal bus.
A wide area network using telephones and an Asynchronous Transfer Mode switching system (ATM) have a hub and spoke type topology, but an objected physical area, a device scale, a timing request, etc. are largely different and is essentially different on a concept to a bus exchange.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a bus emulation apparatus installed on an LSI or a print circuit board and replaceable by a parallel bus.
A second object of the present invention is to provide a bus emulation apparatus capable of transferring data between other peripheral circuits while transferring data between peripheral circuits.
According to the present invention, there is provided a bus emulation apparatus comprising: a hub circuit; a plurality of serial interface circuits; and serial transfer paths for connecting the plurality of serial interface circuits and the hub circuit and being installed on a large scale integrated circuit or a print circuit board, the serial interface circuit comprising: a parallel to serial conversion circuit for converting parallel data from a peripheral circuit connected to the serial interface circuit to a serial data and supplying to the serial transfer path; and a serial to parallel conversion circuit for converting serial data supplied from the hub circuit via the serial transfer path to a parallel data and supplying to the peripheral circuit; and the hub circuit supplying the serial data supplied from the serial interface circuit via the serial transfer path to a serial interface circuit connected to a peripheral circuit as a transfer destination of the parallel data among the plurality of serial interface circuits via the serial transfer path.
Preferably, the hub circuit divides the plurality of serial interface circuit into a plurality of groups for performing data transfers in advance and relays the serial data between the serial interface circuits so that parallel data is transferred in the respective plurality of groups.
Preferably, the serial data supplied from the serial interface circuit to the hub circuit via the serial transfer path comprises an address information indicating a transfer destination; and the hub circuit supplies the serial data to the serial interface circuit connected to a peripheral circuit as the transfer destination based on the address information.
Preferably, the hub circuit comprises a buffer for storing serial data supplied from the serial interface circuit via the serial transfer path; an extraction circuit for extracting address information included in the serial data; a control circuit for determining transfer priority when a plurality of transfer requests exist to a same transfer destination; and a selection circuit for selecting a transfer path of the serial data based on the address information extracted by the extraction circuit and the priority determined by the control circuit.
Alternately, it may be configured that the hub circuit further comprises a detection circuit for detecting transfer end of the serial data form the serial interface circuit and/or an interrupt by the serial interface circuit; and the control circuit determines the priority based on a detection result of the detection circuit.
Alternately, it may be configured that the hub circuit further comprises a clock signal generation circuit for generating a plurality of clock signals having different clock frequencies; and the buffer receives a clock signal from the clock signal generation circuit in accordance with a transfer rate of a peripheral circuit as a transfer source or a transfer destination and inputs/outputs the serial data at a transfer rate in accordance with the supplied clock signal.
Preferably, the hub circuit comprises DMA controllers for controlling transfers of the serial data between the serial interface circuits corresponding to each of the plurality of serial interface circuits.
Preferably, the hub circuit supplies a clock signal to the serial interface circuit via the serial transfer path; and the serial interface circuit supplies the clock signal supplied from the hub circuit to a peripheral circuit operating based on the clock signal and connected to the serial interface circuit.
Alternately, it may be configured that the serial interface circuit comprises a counter for counting the number of data in the buffer in the hub circuit; stops the transmitting the serial data to the hub circuit when a counter value of the counter indicates that the buffer has no vacancy, and transmits the serial data to the hub circuit when the count value of the counter indicates that the buffer has a vacancy.
More preferably, the serial interface circuit, when the parallel data of this time supplied from the peripheral circuit is exactly identical or substantially identical with the preceding parallel data, generates a flag indicating the exactly identity or substantially identity and supplies the generated flag to the hub circuit; and the hub circuit comprises a cache memory for storing preceding serial data corresponding to the preceding parallel data and generates serial data of this time corresponding to the parallel data of this time based on the serial data stored in the cache memory and the flag.
Alternately, it may be configured that the serial interface circuit detects that a difference between the preceding parallel data and the parallel data of this
Dang Khanh
Frommer William S.
Frommer & Lawrence & Haug LLP
Smid Dennis M.
Sony Corporation
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