Electronic digital logic circuitry – Tri-state
Patent
1995-07-11
1996-12-17
Westin, Edward P.
Electronic digital logic circuitry
Tri-state
326 86, 326 93, 326 9, H03K 19096, H03K 19003
Patent
active
055857426
ABSTRACT:
In a bus system of a computer, an enable pulse is propagated through different signal paths and bus drivers so that it takes different amounts of time to reach a common bus. Each bus driver has a tristate output buffer connected to the bus, a delay circuit and an AND gate for receiving an enable pulse from one of the signal paths. The input terminal of the delay circuit is also connected to receive the same enable pulse for introducing a predetermined amount of delay to the enable pulse and supplying the delayed pulse to the AND gate, so that the delayed pulse is truncated at the trailing edge of the enable pulse directly supplied to the AND gate. The output terminal of the AND gate is connected to the enable/disable input terminal of the tristate output buffer for enabling it with the delayed and truncated enable pulse. The amounts of delays introduced in the bus drivers are manually set so that the delayed pulses would arrive at nearly the same time at the respective output buffers if they were simultaneously transmitted.
REFERENCES:
patent: 4945264 (1990-07-01), Lee et al.
patent: 5225723 (1993-07-01), Drako et al.
Driscoll Benjamin D.
NEC Corporation
Westin Edward P.
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