Electronic digital logic circuitry – Interface – Current driving
Patent
1995-09-26
1996-10-15
Hudspeth, David R.
Electronic digital logic circuitry
Interface
Current driving
326 30, 326 31, 326 83, H03R 1716
Patent
active
055657966
ABSTRACT:
To obtain a bus system capable of saving power consumption without increasing the number of data lines. In precharge period, by charging and discharging by data line drive circuits (23p, 23n), potentials of data lines (30, 31) of a bus (1) are set to power source potential (VDD) and grounding potential (GND), respectively. In equalizing period, by connecting the data lines (30, 31) by a switch (3), the potentials of the data lines (30, 31) are set to an intermediate potential of the power source potential (VDD) and grounding potential (GND). In data transfer period, by selectively connecting between data line (3) and power source line, and between data line (31) and grounding line, by means of data line drive circuits (23p, 23n), the signals transmitted through the data lines (30, 31) are caused to swing between the intermediate potential and power source potential (VDD), and between the intermediate potential and grounding potential (GND). A receiver circuit (25) converts the transmitted signal into a signal swinging between the power source potential (VDD) and grounding potential (GND).
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1994 Symposium on VLSI Circuits Digest of Technical Papers, pp. 21-22, 1994, H. Yamauchi, et al., "A Low Power Complete Charge-Recycling Bus Architecture for Ultra-High Data Rate ULSI'S".
1994 Symposium on VLSI Circuits Digest of Technical Papers, pp. 23-24, H. Kojima, et al., "Half-Swing Clocking Scheme For 75% Power Saving In Clocking Circuitry".
1994 Symposium on VLSI Circuits Digest of Technical Papers, pp. 29-30, 1994, M. Hiraki, et al., "Data-Dependent Logic Swing Internal Bus Architecture for Ultra-Low-Power LSIs".
Hudspeth David R.
Mitsubishi Denki & Kabushiki Kaisha
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