Bus device that concurrently synchronizes source synchronous...

Details Bus device that concurrently synchronizes source synchronous... Bus device that concurrently synchronizes source synchronous...

2006-11-21

2006-11-21

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S701000

Reexamination Certificate

active

07139965

ABSTRACT:
A bus device comprises a clock generator that is adapted to generate a clock signal for internal use by the bus device, data synchronizing logic that is adapted to synchronize source synchronous data that the bus device receives from the bus to the bus device's clock signal, and error detection and correction logic coupled to the data synchronizing logic. The error detection and correction logic is adapted to detect and correct errors associated with the data received from the bus concurrently while the data synchronizing logic synchronizes source synchronous data received from the bus to the clock signal.

REFERENCES:
patent: 3550082 (1970-12-01), Tong
patent: 6829715 (2004-12-01), Chiao et al.
patent: 6915446 (2005-07-01), Riley

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