Bus controller and information processing device providing reduc

Details Bus controller and information processing device providing reduc Bus controller and information processing device providing reduc

1997-03-20

1999-06-29

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710104, 710 61, 713401, G06F 1314

Patent

active

059163119

ABSTRACT:
A bus controller controls an access to a bus connected to a first device which operates in synchronization with a first clock signal and a second device which operates in asynchronization with the first clock signal. The controller includes a detector. The detector receives an access request from a central processing unit which operates in synchronization with a second clock signal different from the first clock signal to detect whether the access request represents an access to the first device or an access to the second device. The controller further includes an access controlling signal generator. The access controlling signal generator generates a first access controlling signal for controlling an access of the first device to the bus in synchronization with the first clock signal and for supplying the first access controlling signal to the first device, in a case where the access request represents the access to the first device. The access controlling signal generator generates a second access controlling signal for controlling an access of the second device to the bus in synchronization with the second clock signal and for supplying the second access controlling signal to the second device, in a case where the access request represents the access to the second device.

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