Bus control system

Details Bus control system Bus control system

2007-02-13

2007-02-13

Perveen, Rehana (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S305000

Reexamination Certificate

active

10274881

ABSTRACT:
In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

REFERENCES:
patent: 3997896 (1976-12-01), Cassarine, Jr. et al.
patent: 4128883 (1978-12-01), Duke et al.
patent: 4232366 (1980-11-01), Levy et al.
patent: 4281380 (1981-07-01), DeMesa, III et al.
patent: 4290102 (1981-09-01), Levy et al.
patent: 4543628 (1985-09-01), Pomfret
patent: 4672662 (1987-06-01), Nishino et al.
patent: 4785394 (1988-11-01), Fischer
patent: 4797815 (1989-01-01), Moore
patent: 4821174 (1989-04-01), Webb et al.
patent: 4941088 (1990-07-01), Shaffer et al.
patent: 4953072 (1990-08-01), Williams
patent: 5001625 (1991-03-01), Thomas et al.
patent: 5146597 (1992-09-01), Williams
patent: 5191649 (1993-03-01), Cadambi et al.
patent: 5235684 (1993-08-01), Becker et al.
patent: 5237567 (1993-08-01), Nay et al.
patent: 5274787 (1993-12-01), Hirano et al.
patent: 5341495 (1994-08-01), Joyce et al.
patent: 5379384 (1995-01-01), Soloman
patent: 5388224 (1995-02-01), Maskas
patent: 5414820 (1995-05-01), McFarland et al.
patent: 5483642 (1996-01-01), Okazawa et al.
patent: 5594880 (1997-01-01), Moyer et al.
patent: 6128688 (2000-10-01), Kondo et al.
patent: 6584538 (2003-06-01), Kondo et al.
patent: 1-161461 (1989-06-01), None
patent: 2-161551 (1990-06-01), None
patent: 3-102558 (1991-04-01), None
patent: 3-222543 (1991-10-01), None
patent: 3-278156 (1991-12-01), None
patent: 3-288957 (1991-12-01), None
patent: 3-102558 (1992-04-01), None
“Futurebus+ P896.1: Logical Layer Specifications”, IEEE, 1990, pp. 89-90.
J.A. Gallant, “Futurebus+”, EDN, Oct. 1, 1990, pp. 87-98.
J. Cantrell, “Futurebus+ Cache Coherence”, WESCON '89 Conference Record, Nov. 14-15, 1989, pp. 602-607.
Langendoen et al, “Evaluation of Futurebus Hierarchical Caching”, vol. 1, PARLE '91—Parallel Architectures and Language Europe, 1991, pp. 52-68.
M. Azimi et al, “Design and Analysis of a Hierarchical Snooping Cache Coherence System”, Proceedings of the 27th Annual Allerton Conference on Communication, Control and Computing, vol. 1, 1988, pp. 109-118.

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