Bus control circuit

Details Bus control circuit Bus control circuit

2002-09-06

2004-09-28

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S027000, C326S088000, C327S170000, C327S108000

Reexamination Certificate

active

06798235

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to bus control circuits, and more particularly to a bus control circuit including a switching time servo system.
2. Description of the Related Art
Communication systems continuously develop and operation speeds increase constantly. Bus control circuits—also called bus drivers or bus buffers—operate at increasingly higher speeds.
A typical example is provided by the serial interface defined in the CCITT standard, Universal Serial Bus, which is intended to control operation of the serial interface between data processing systems, and in particular between computer devices. In one of the latest versions of this standard—i.e., standard known as USB 2.0—bus control circuits are designed to operate at three different speeds namely, low speed, full speed and high speed. Full speed is considered to be 12 Mbits per seconds and this standard imposes particularly severe constraints in particular regarding switching times of both output circuits (or “buffers”) driving the serial cable.
FIG. 1
shows a conventional architecture for such a control circuit comprising a twin control circuit having a low impedance—typically 6 ohms—for example switching to 6 MHz for 50 picoFarads capacitive loads.
A first control circuit or driver
100
is based on a pair of NMOS-PMOS transistors comprised of a PMOS transistor
10
and a NMOS transistor
20
, respectively, the drains of these transistors are connected to a common D+ electrode. Each one of transistors
10
and
20
has a coupling capacitor—
11
and
21
respectively—which makes it possible to set to an absolute value the rise and decay times of terminal D+ output potential fed by a capacitor C
LP
15
. A respective current generator, respectively
12
and
22
, controls the gates of transistors
10
and
20
.
Similarly, the control circuit comprises a second circuit
200
which is also based on a pair of NMOS-PMOS transistors comprised of transistors
30
and
40
, controlled by power sources
32
and
42
respectively, and associated with a coupling capacitor,
31
and
41
respectively. The common junction of PMOS transistor
30
and NMOS transistor
40
provides a potential D−, to which a (presumably capacitive) load C
LP
35
is connected, and potential D− is supposed to switch exactly contrary to the common potential D+ of transistors
10
and
20
.
The assembly of circuits
100
and
200
makes up a twin control structure for a bus. It is however apparent that characteristics of the NMOS and PMOS transistors are difficult to pair to generate virtually identical rise and decay times for potentials D+ and D. Pairing NMOS and PMOS transistors so that they show substantially similar internal characteristics, as is currently done, for example, with resistors or capacitors is one of the great difficulties encountered in manufacturing processes.
BRIEF SUMMARY OF THE INVENTION
An embodiment of this invention provides a solution to the problem of designing a simple structure for a control circuit that allows for compensation of differences between active components, and particularly NMOS and PMOS components, and to appreciably pair the switching times of transistors, in particular their rise and decay times.
An embodiment of the present invention provides a control or interfacing structure for a serial cable having virtually identical rise and decay time values.
An embodiment of the invention is directed to a bus interface circuit that comprises:
a first circuit comprising a first pair of transistors of opposite types having a control electrode and a common electrode for providing a first output potential (D+);
a second circuit comprising a second pair of transistors of opposite types and having a common electrode for providing a second potential (D−) switching in opposite direction from the former;
first capacitive coupling means for feeding a portion of the signal existing at said first potential (D+) back into said control electrodes of said second pair of transistors and,
second capacitive coupling means for feeding a portion of the signal existing at said second potential (D−) back into said control electrodes of said first pair of transistors, in order to compensate for the internal characteristics of the transistors and to standardize rise and decay times.
Preferably, coupling will be carried out by cross coupling capacitors and it will then be possible, by simply pairing the capacitors, which is easy to carry out, to compensate for variations of the internal characteristics of the NMOS and PMOS transistors and to obtain identical rise and decay times.
In a preferred embodiment, the first pair of transistors comprises a PMOS-type first transistor, having a source electrode connected to a positive potential (V+) and having a gate that receives a control signal. An NMOS-type second transistor has a source electrode connected to a negative potential (V−) and also has a gate receiving a control signal. Both drain electrodes of the first and second transistors are connected together so as to provide a potential to the output electrode (D+). A first coupling capacitor is respectively connected between the gate and drain of the first transistor and, in the same way, a second coupling capacitor is inserted between the gate and the drain of the second transistor. Cross capacitive coupling is then realized by means of first and second cross coupling capacitors, having one electrode connected to the output (D−) potential of the second control circuit and a second electrode respectively connected to the gate of the first transistor and the gate of the second transistor.
The second circuit comprises a PMOS-type third transistor having a gate and having a source electrode connected to a positive potential (V+). The third transistor is serially assembled to a NMOS-type fourth transistor having a source electrode connected to a negative potential (V−) and having a common drain electrode with the third transistor, this common electrode being connected to the output potential (D−). A NMOS-type fourth transistor has a source electrode connected to a negative potential (V−) and its gate receives a control signal. A third output coupling capacitor is connected between the gate and the drain of the third transistor and, in the same way, a fourth output coupling capacitor is connected between the gate and the drain of the fourth transistor.
Cross capacitive coupling is then realized by means of third and fourth cross coupling capacitors, each having a first electrode connected to the output potential (D+) of the first control circuit and a second electrode that is connected to the gate of the third and the gate of the fourth transistor respectively.
In a preferred embodiment, values of the four cross coupling capacitors C
1
, C
2
, C
3
and C
4
will be set according to the following formulas:
C
1
=K×C
2
C
3
=C
1
C
4
=C
2
where K corresponds to the ratio of the bias current values in sources
12
and
42
respectively.
Alternatively, a dual structure can be realized in which the first, second, third and fourth transistors are NMOS, PMOS, NMOS and PMOS transistors respectively.
Preferably, the control circuit will be associated with a device for avoiding simultaneous conduction of the transistors of the first and second pairs in order to avoid power overdrain.
In a preferred embodiment, cross coupling capacitors between the first and second circuits will advantageously be realized by means of manufacturing techniques based on capacity arrays


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