Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-03-04
2001-05-01
Sheikh, Ayaz R. (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S105000, C710S011000, C710S016000, C710S056000, C710S241000
Reexamination Certificate
active
06226702
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally related to a bus control method, a bus control apparatus, and also a storage medium for storing thereinto a bus control program. More specifically, the present invention is directed to bus control method/system capable of controlling such that which bus is allocated to which data input/output means (memory, LAN board, modem etc) in response to a bus allocation request issued from the respective data input/output means in a control system where a plurality of data input/output means are connected to the buses, and further directed to a storage medium for storing thereinto a bus control program.
2. Description of the Related Art
The above-described sort of bus control apparatus is known in this field. For example, Japanese Paten Laid-open t Application No. Hei-6-332841 published in 1994 discloses the bus control apparatus which is applied to a computer system. That is,
FIG. 12
is a schematic block diagram for representing an internal arrangement of this conventional computer system.
This sort of computer system is mainly arranged by a CPU (central processing unit)
1
, a memory
2
, a plurality of data input/output means
3
to
5
, and a bus control apparatus
6
. These structural elements are connected via a bus
7
to each other.
In the case that the CPU
1
and these data input/output means
3
to
5
(will be collectively referred to as a “device” hereinafter) request to access the memory
2
and other devices via the bus
7
, the CPU
1
and the data input/output means
3
to
5
supply allocation request signals REQ
1
to REQ
4
to the bus control apparatus
6
, respectively. As a result, in order to avoid such a risk that a plurality of devices will make simultaneous accesses via the bus
7
, the bus control apparatus
6
determines which device may be allowed to be accessed via the bus
7
. Then, this bus control apparatus
6
supplies allocation permission signals GNT
1
to GNT
4
to the determined device. Such a device to which the allocation permission signal GNT is supplied accesses via the bus
7
the memory
2
, or another device. When this access operation is accomplished, this device supplies an end signal DON to the bus control apparatus
6
. Also, when the bus control apparatus
6
detects an error while investigating which device is allowed to be allocated via the bus
7
, this bus control apparatus
6
supplies an error signal ERR to the CPU
1
.
Although not shown in this drawing, the bus control apparatus
6
is mainly implemental by an arbiter controller, an arbiter memory, and a history register.
When any one of the allocation request signals REQ
1
to REQ
4
is supplied to the arbiter controller, this arbiter controller supplies 4-bit data (request bit) to the arbiter memory as low-order bits of an address of the arbiter memory. This 4-bit request data is formed by setting “1” to the bits corresponding to the supplied allocation request signal REQ. On the other hand, the past allocation permission histories as to the respective devices are stored in a first-in-first-out (FIFO) manner into the history register. In this example, since only one device is allowed to be allocated at a time, this past allocation permission history is constituted by 4 sets of data immediately close to the 4-bit data, namely 16-bit data. This 4-bit data is formed by setting “1” only to the bits corresponding to the allocation-permitted device. This past allocation permission history is supplied to the arbiter memory as an higher order bit of the address of the arbiter memory.
In this arbiter memory, the various algorithms are stored. That is, a priority order allocation permission algorithm and another allocation permission algorithm such as the round robin algorithm are stored. This priority order allocation permission algorithm corresponds to various combinations between the present allocation requests (request bits) supplied from the respective devices and the past allocation permission histories supplied from the history register. In other words, this priority order allocation permission algorithm implies that while priority orders are previously applied to a plurality of devices connected to a bus, when allocation request signals REQ are simultaneously supplied from a plurality of devices, only such a device having a top priority order is allowed to be allocated.
On the other hand, the round robin algorithm corresponds to such an algorithm that until allocation permissions for all of devices are accomplished one time, when allocation request signals REQs are simultaneously supplied from a plurality of devices, allocation permissions are applied to such devices which have not yet received the allocation permissions in the past. After the allocation permissions for all of these devices are ended one time, in such a case that the allocation request signals REQs are supplied from these plural devices at the same time, the allocation permission is applied to a device to which the allocation permission has been given in the earliest stage of the first cycle, while having a top priority.
As a result, since the allocation permission corresponding to the supplied 20-bit data is read out from the arbiter memory, the arbiter controller supplies the allocation permission signal GNT to any one of these devices based on the read allocation permission. At this time, the now read allocation permission is stored as the latest allocation permission into the history register in the FIFO manner. It should be understood that a portion of the past allocation permission stored in the history register may be varied by the respective devices.
With employment of such an arrangement, the arbiter controller can accept the allocation requests issued from the respective devices in the time-to-time manner, while maintaining the flexible characteristics thereof. Therefore, the arbiter controller can effectively use the bus.
In the above-explained conventional bus control apparatus, as the high-order bit of the address of the arbiter memory, 4 sets of allocation permissions provided immediately close to each other are used, and further, as the lower-order bit of the address of the arbiter memory, the present allocation requests (request bits) issued from the respective devices are used to select the allocation permission. In this arbiter memory, the allocation permission algorithm is stored, whereas the 4 sets of allocation permissions are stored into the history register. In this specification, the expression “4 sets of allocation permissions immediately provided with each other” implies such a record that an allocation is permitted one time to each of these devices. As a consequence, a total number of devices connectable to a bus would be limited to a bit number of an address of an arbiter memory. Accordingly, in the above-explained conventional bus control apparatus, the total bit number of the history register is required by such a number defined by adding the required bit number to 2-power of a total number of these devices. It should be noted that the required bit number is equal to the total number of these devices.
Therefore, in order that a user may freely add any devices to a computer system, namely higher flexibility, it is required to employ such an arbiter memory having a bit number equal to a total number of devices connectable to a bus. Furthermore, extra storage regions of a history register would be increased in an exponential manner every time even one device is additionally introduced. For example, when 8 sets of devices in maximum are designed to be connectable with a bus, the history register would require the storage regions capable of storing 72-bit data, and the address of the arbiter memory would become 8 bits, namely 256 words. In such a case, even when this user connects only 4 sets of devices to the bus, the necessary allocation permission algorithm must be previously stored in the arbiter memory, assuming now that 8 sets of devices are in principle connected to this bus. Moreover, the a
Foley & Lardner
NEC Corporation
Phan Raymond N
Sheikh Ayaz R.
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