Electrical computers and digital data processing systems: input/ – Input/output data processing – Data transfer specifying
Reexamination Certificate
2000-01-27
2004-03-16
Vo, Tim (Department: 2189)
Electrical computers and digital data processing systems: input/
Input/output data processing
Data transfer specifying
C710S031000, C710S107000, C710S316000
Reexamination Certificate
active
06708236
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bus control apparatus for efficiently controlling data of an image input apparatus such as a scanner and an image output apparatus such as a printer.
2. Description of the Related Art
There has conventionally been put to practical use an image processing apparatus called a digital composite appliance such as a copying machine or facsimile which is equipped with a combination of an image input apparatus such as a scanner and an image output apparatus such as a printer, or a computer system which is equipped with an image input apparatus and image output apparatus as separate component units. To realize composite functions such as an image input function, image output function, and copying function in this image processing apparatus, when the image input apparatus and image output apparatus cannot operate in synchronization with each other, the copying function is realized by outputting, to the image output apparatus, image data temporarily stored from the image input apparatus in a memory. When the image input apparatus and image output apparatus can operate in synchronization with each other, the copying function is realized by disposing a passage for directly transferring an image signal from the image input apparatus to the image output apparatus.
However, image data often has a very large size, and requires a mechanism for transferring data between, e.g., an image input apparatus, memory, and image output apparatus at a high speed. In addition, the image size to be transferred changes, and the bus width used to transfer image data does not match the boundary of image data in many cases. If a mechanism for performing data transfer matching the boundary of image data is disposed on an image transfer bus, the mechanism decreases the bus transfer speed.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation, and has as its object to provide a bus control apparatus capable of realizing both high-speed image data transfer and image data transfer matching the boundary of image data.
To achieve the above object, according to the present invention, data is transferred using the first bus when data matching the bus width is to be transferred, and using the second bus when data not matching the bus width is to be transferred.
The present invention comprises the following arrangement. That is, a bus control apparatus which is connected to first and second buses each connected to a memory, and control means for determining which of the first and second buses can be used, and selecting the determined bus to transfer data.
It is preferable that the first bus have a burst transfer mode without having any single transfer mode, and the second bus have a single transfer mode.
When a transfer destination memory address or a data length to be transferred does not match a burst transfer unit of the first bus, the control means preferably selects the second bus.
The control means preferably performs two-dimensional DMA transfer for transferring image data to a memory space having a predetermined size.
The control means for the first and second buses is preferably integrated on a semiconductor substrate.
Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof.
REFERENCES:
patent: 5179663 (1993-01-01), Iimura
patent: 5542110 (1996-07-01), Minagawa
patent: 5628026 (1997-05-01), Baron et al.
patent: 5748921 (1998-05-01), Lambrecht et al.
patent: 6006289 (1999-12-01), James et al.
patent: 6088743 (2000-07-01), Takeda
patent: 6145028 (2000-11-01), Shank et al.
patent: 1022896 (2000-07-01), None
Microsoft Press, “Computer Dictionary”, 1997 Third Edition, p. 255.
Date Atsushi
Fujiwara Takafumi
Kato Katsunori
Maeda Tadaaki
Yokoyama Noboru
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