Bus construction

Details Bus construction Bus construction

1999-09-03

2002-05-28

Thai, Xuan M. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Protocol

C710S315000, C710S316000

Reexamination Certificate

active

06397278

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates to a bus construction for connecting a circuit controlled via a separate control port to a bus controlled by addressing.
2. Discussion of Related Art
In the technical world of today, people use more and more electronic devices in their everyday life. Almost all modern products of consumer electronics contain a microprocessor that controls the device. The microprocessor can be connected to the other integrated circuits of the device by using a known bus construction. One of the most common bus constructions is the I
2
C bus as described in “Philips Semiconductors, 80C51-Based 8-bit Microcontrollers”, Book IC20 1994, Philips, pages 1141-1159, and other bus constructions controlled by addressing. The I
2
C bus comprises DATA and CLOCK signal paths, through which the control commands according to the I
2
C standard are sent to the circuits connected to the I
2
C bus to control the circuits.
However, not all integrated circuits support a bus construction controlled by addressing. For example, the control of phase-locked loops is generally implemented by means of a control signal brought to the control port of the circuit via a separate signal path. A solution like this can be implemented, for example, as a 3-wire or IM bus solution based on three signal paths, as described in “Fernsehtechnik ohne Ballast”, Otto Limann/Horst Pelka, ISBN 3-7723-5723-7, Franzis-Verlag GmbH, 1993, pp. 498-503. The instruction set of circuits controlled via a separate control port differs from the instruction set of circuits controlled by addressing. Because of this, in prior art systems in which there are both circuits that are controlled by addressing and circuits controlled by a separate control port, the buses are typically separated from each other, for example like in FIG.
1
.
In the prior art solution shown in
FIG. 1
, an I
2
C bus
12
controlled by addressing connects the microprocessor
11
by means of two signal paths (DATA, CLOCK) to the first and the second I/O circuit
15
and
16
, and a 3-wire bus
13
based on a separate control signal connects the microprocessor
11
by three signal paths (DATA, CLOCK, ENABLE) to the phase-locked loop
14
. If many separately controlled circuits were connected to the bus
13
, each one would need its own ENABLE, i.e. control, signal path. The I
2
C bus
12
is connected to the first I/O ports
17
of the microprocessor
11
, and the 3-wire bus
13
is connected to the second I/O ports
18
of the microprocessor. Thus the microprocessor can control each bus
12
and
13
separately, and the signals of one bus cannot interfere with the operation of the other bus.
In order to simplify the construction of electronic devices and the program that controls the microprocessor, it is a general objective to minimize the number of signal paths and thereby also the number of I/O ports to the processor. In accordance with the prior art described above, each bus type is given its own I/O port and signal path.
SUMMARY OF INVENTION
The purpose of this invention is to achieve a new bus construction, which enables connecting circuits of different standards to the same path, whereby the number of the signal paths used and the number of the I/O ports used of the processor can be reduced in comparison to the prior art solution. The objectives are achieved by connecting the signal paths connected to the CLOCK and DATA inputs of the circuit controlled by a separate control port, such as a 3-wire circuit, via switches to the corresponding signal paths of a bus controlled by addressing, such as an I
2
C bus.
The bus construction according to the invention is characterized in what is set forth in the characterizing part of claim
1
. The preferred embodiments of the invention are described in the dependent claims.
Compared to the prior art, the invention has the advantage of simplifying the bus construction of the device by reducing the number of the signal paths and I/O ports of the processor in use.
Furthermore, the invention provides the possibility to separate the signal paths of different buses by means of analog switches, whereby a circuit controlled by a separate control port can be disconnected from the bus construction controlled by addressing, whereby the signals directed to circuits that use addressing cannot get to the I/O ports of the circuit controlled via a separate control port. In this way, signal interference in the operation of the circuit is avoided, and therefore the use of switches improves the reliability of the device compared to a solution in which signal paths according to different standards are connected without switches.


REFERENCES:
patent: 5376928 (1994-12-01), Testin
patent: 5812802 (1998-09-01), Bahout et al.
patent: 5884044 (1999-03-01), Marsanne et al.
patent: 5892933 (1999-04-01), Voltz
patent: 6092138 (2000-07-01), Schutte
patent: 0759593 (1997-02-01), None
patent: 0769748 (1997-04-01), None
patent: 5-308392 (1993-11-01), None
“The I2C-bus and how to use it”, Philips Semiconductors 80C51-Based 8-Bit Microcontrollers, Jan. 1992, pp. 1141-1159.

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