Bus configuration and input/output buffer

Details Bus configuration and input/output buffer Bus configuration and input/output buffer

1996-11-21

1999-09-07

Santamauro, Jon

Electronic digital logic circuitry

Interface

Current driving

326 30, 326 87, H03K 190185

Patent

active

059492520

ABSTRACT:
A system for signal transmission has at least one bus for the signal transmission and a reflection-prevention resistance provided on a stub connected to the bus for preventing reflection of signals at an intersection between the bus and the stub. The system includes termination resistances, and a switch unit for coupling the bus to termination voltage via the termination resistances in a first mode and for disconnecting the bus from the termination voltage in a second mode.

REFERENCES:
patent: 5239658 (1993-08-01), Yamamuro et al.
patent: 5274671 (1993-12-01), Johnson
patent: 5479123 (1995-12-01), Gist et al.

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