Bus configuration and input/output buffer

Details Bus configuration and input/output buffer Bus configuration and input/output buffer

1999-06-25

2000-11-28

Santamauro, Jon

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

326 86, H03K 190175

Patent

active

061540471

ABSTRACT:
A system for signal transmission has at least one bus for the signal transmission and a reflection-prevention resistance provided on a stub connected to the bus for preventing reflection of signals at an intersection between the bus and the stub. The system includes termination resistances, and a switch unit for coupling the bus to termination voltage via the termination resistances in a first mode and for disconnecting the bus from the termination voltage in a second mode.

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patent: 5239658 (1993-08-01), Yamamuro et al.
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patent: 5382841 (1995-01-01), Feldbaumer
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patent: 5602494 (1997-02-01), Sundstrom
patent: 5731711 (1998-03-01), Gabara
patent: 5781028 (1998-07-01), Decuir

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