Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2002-04-09
2004-07-20
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S030000, C326S090000, C716S030000, C710S100000, C710S120000
Reexamination Certificate
active
06765413
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bus circuit, in particular, to a bus circuit which includes a plurality of signal lines.
2. Description of the Background Art
A semiconductor integrated circuit device is formed of a plurality of circuit blocks represented by an operation unit or a memory. Data exchange among circuit blocks within the semiconductor integrated circuit device is, in general, carried out by using a signal line.
FIG. 11
is a block diagram of a conventional bus circuit within a semiconductor integrated circuit device.
Referring to
FIG. 11
, a plurality of circuit blocks
3
, respectively, have input/output circuits
2
. Respective input/output circuits
2
are connected to a signal line
1
. Input/output circuits
2
include drivers
6
and receivers
7
. Drivers
6
output data from circuit blocks
3
to signal line
1
. Receivers
7
receive data from signal line
1
. Here, though three circuit blocks are shown in
FIG. 1
, a plurality of additional circuit blocks may be included.
In order to prevent a plurality of circuit blocks
3
from transmitting data at the same time, circuit blocks
3
cannot transmit data unless the usage right for signal line
1
is acquired. Arbitration of the usage right of the signal line
1
among the circuit blocks is carried out by a dedicated control circuit (not shown).
In
FIG. 11
, circuit blocks
3
which have, respectively, one input/output circuit
2
are connected to one signal line
1
. 1 bit of data is transmitted on one signal line. Conventionally, a data processing unit of a circuit block
3
is not 1 bit but is 32 bits, or more. Accordingly, in practice there are 32, or more, signal lines
1
within the bus circuit and a circuit block
3
has a plurality of input/output circuits
2
connected to respective signal lines.
In recent years the process dimensions of a semiconductor integrated circuit device have become scaled and, as a result, the amount of data which can be processed by a circuit block
3
within the bus circuit at one time has increased from 32 bits to 64 bits or, further, to 128 bits, or more.
FIG. 12
is a circuit diagram of a driver
6
in FIG.
11
.
Referring to
FIG. 12
, driver circuit
6
includes inverters
62
,
63
, a NAND gate
61
and a NOR gate
64
. Inverter
62
includes a P channel MOS transistor
621
and an N channel MOS transistor
622
. A driver signal EN is a signal which is inputted to NAND gate
61
and is inputted to NOR gate
64
via inverter
63
and is a signal which is inputted from the outside in order to activate driver
6
.
In a circuit block
3
which has acquired the bus usage right, driver activation signal EN is set to an active condition (H level). Therefore, driver
6
outputs a signal of H level from driver
62
when data signal D is at H level and outputs a signal of L level when data signal D is at L level. In addition, in a circuit block
3
which has not acquired the bus usage right, driver activation signal EN is set at L level. Therefore, P channel MOS transistor
621
and N channel MOS transistor
622
in driver
6
are both turned off and, as a result, driver
6
is converted to a high impedance condition.
On the other hand, a receiver
7
receives the entirety of the data on signal line
1
. The received data is transmitted to circuit block
3
and the circuit block determines whether or not the received data is utilized. Through the above operation, data exchange is carried out among circuit blocks
3
within the bus circuit.
FIG. 13
is a circuit diagram showing
3
signal lines for transmitting data signals among a plurality of signal lines within the bus circuit.
Referring to
FIG. 13
, a signal line BUS
2
is a signal line neighboring signal lines BUS
1
and BUS
3
. Signal line BUS
2
transfers a data signal D, signal lines BUS
1
transfers a data signal D
n−1
and signal lines BUS
3
transfers a data signal D
n+1
, respectively. In addition, drivers DR
1
to DR
3
are, respectively, connected to one end of signal lines BUS
1
to BUS
3
. Furthermore, receivers RV
1
to RV
3
are, respectively, connected to the other end of signal lines BUS
1
to BUS
3
.
Here, the wire capacitance which is driven when driver DR
2
outputs data signal D
n
to signal line BUS
2
is described.
First, the case where data signals D
n+1
and D
n−1
change while in a phase opposite to that of data signal D
n
is described.
At this time, capacitance Cm between wires for data signal D
n
and data signal D
n+1
appears twice as large as it actually is due to the Miller effect because when the potential of capacitance Cm between wires at one terminal C
1
changes from power source potential VDD to ground potential GND, the potential of capacitance Cm between wires at the other terminal C
2
changes from ground potential GND to power source potential VDD. Therefore, the amount of relative potential change from terminal C
1
to terminal C
2
becomes 2VDD.
In the same manner, capacitance Cm between wires for data signal D
n
and D
n−1
appears twice as large as it actually is.
From the above, a wire capacitance Cn that must be driven in order for driver DR
2
to output data signal D
n
onto signal line BUS
2
is given in the following equation (1).
Cn=
2
Cm+
2
Cm+CL=
4
Cm+CL
(1)
wherein CL is a capacitance between the signal line and the ground.
Next, the case where data signals D
n+1
and D
n−1
change while in the same phase as that of data signal D
n
is described.
At this time, potential difference between terminals of capacitance Cm between wires does not occur. Accordingly, wire capacitance Cn that must be driven in order for driver DR
2
to output data signal D
n
onto signal line BUS
2
is given in the following equation (2).
Cn=CL
(2)
Next, the case where data signals D
n+1
and D
n−1
do not change and only data signal D
n
changes is described.
At this time, the Miller effect does not occur with capacitance Cm between wires. Accordingly, wire capacitance Cn that must be driven in order for driver DR
2
to output data signal D
n
onto signal line BUS
2
is given in the following equation (3).
Cn=Cm+Cm+CL=
2
Cm+CL
(3)
In the conventional bus circuit, since capacitance CL between the signal line and the ground is larger than capacitance Cm between wires, the transmission speed of a data signal is not affected by a change of a data signal on the neighboring signal line. However, in recent years, miniature processing technology for signal lines has progressed and, therefore, signal line pitches have become narrower. As a result, capacitance Cm between wires has become larger than capacitance CL between the signal line and the ground.
Here, a change of transmission speed of a data signal in the case that a data signal on a neighboring signal line has changed relative to data signal D
n
on signal line BUS
2
in
FIG. 13
is described.
The amount of time for data signal D
n
to change from power source potential VDD or ground potential GND to VDD/2 is defined as a data signal transmission time &Dgr;t. Data signal transmission time &Dgr;t is approximated in the next equation (4).
&Dgr;
t=VDD×Cn/ID/
2 (4)
wherein ID is an average current driving force of the driver.
For example, it is assumed that capacitance Cm between wires/ground capacitance CL is 2. In the case that data signals D
n+1
and D
n−1
change while in a phase opposite to that of data signal D
n
, a data signal transmission time &Dgr;t1 of data signal D
n
is given in the following equation from equations (1) and (4).
&Dgr;
t
1
=VDD×
(4
Cm+CL
)/2
ID
=9
VDD×CL/
2
ID
(5)
In addition, in the case that data signals D
n+1
and D
n−1
change while in the same phase as that of data signal D
n
, a data signal transmission time &Dgr;t2 of data signal D
n
is given in the following equation from equations (2) and (4).
&Dgr;
t
2
McDermott Will & Emery LLP
Renesas Technology Corp.
Tan Vibol
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