Bus capability voting mechanism

Details Bus capability voting mechanism Bus capability voting mechanism

2005-09-06

2005-09-06

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S600000, C710S008000, C710S301000

Reexamination Certificate

active

06941483

ABSTRACT:
A computer system is disclosed having a bus capability determination mechanism. In a preferred embodiment, the computer system includes a backplane having sockets into which system and peripheral boards may be inserted. The sockets are coupled together by a backplane bus that includes a bus capability line. Each board preferably includes a voting circuit that, when enabled, limits the voltage on the capability signal line to no more than a predetermined voltage that is indicative of the capability of the board. The voltage on the capability signal line will thus be determined by the board having the lowest voltage limit. The clock source for the bus can then be set to the clock rate indicated by the voltage on the capability signal line. Zener devices are preferably used to carry out the voting operation, and may be disabled after the voting operation is complete.

REFERENCES:
patent: 5678065 (1997-10-01), Lee et al.
patent: 6510473 (2003-01-01), Voit
patent: 6782438 (2004-08-01), Duncan et al.
“PCI-X: An Evolution of the PCI Bus”; Technology Brief, ISSD Technology Communications, Compaq Computer Corporation, Sep. 1999 (pp. 1-13).

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