Bus bridge transaction checker for correct resolution of combine

Details Bus bridge transaction checker for correct resolution of combine Bus bridge transaction checker for correct resolution of combine

1997-07-31

1999-08-24

Ray, Gopal C.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

395500, 395556, G06F 1338, G06F 1342

Patent

active

059419717

ABSTRACT:
A method to correctly resolve combined data cycles in a bus bridge's posted write buffer is described. In a computer system with a bus bridge connecting a plurality of system buses, a state machine model is created for each bus in the system. A bus cycle state machine object corresponding to an initiated bus cycle is instantiated and stored in at least one of a plurality of cycle list objects. The combine cycle list stores combinable bus cycles and has number of entries equal to the number of entries in the posted write buffer. A pointer may be placed in the combine list upon creation of each combinable bus cycle. For each combinable cycle stored in it, the initiator cycle list searches the combine list for a cycle with an identical address and byte enable, but a later clock cycle number. This later cycle is matched its data with an appropriate target cycle in the target cycle list. Upon finding the data match, the initiator cycle list resolves the combinable initiator cycle. Thus, false failures due to byte collapsing can be eliminated.

REFERENCES:
patent: 5774683 (1998-06-01), Gulick
patent: 5832245 (1998-11-01), Gulick

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