Bus bridge state monitoring in a bus bridge verification system

Details Bus bridge state monitoring in a bus bridge verification system Bus bridge state monitoring in a bus bridge verification system

1997-07-31

1999-10-05

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710 62, 710126, 710128, G06F 1300

Patent

active

059616253

ABSTRACT:
A system for and a method of monitoring the current state of a bus bridge in a device independent manner are disclosed. In a computer system having a bus bridge connecting a plurality of system buses, a bus bridge model object is created with storage space allocated for each of the bus bridge's configuration registers. A CPU write cycle state machine object may send bus cycles intended for the bus bridge to the bus bridge model also. Using the data from these cycles, the model updates its registers accordingly. Thus, the current state of the bus bridge is always known. In one embodiment, bus cycle state machine objects can also poll the bus bridge model object to determine if a bus cycle address is remapped by the bus bridge. Various bus objects, through their state machines, may also poll the bus bridge model for pertinent information. Hence, false failures because of a lack of knowledge of the state of the bus bridge can be eliminated and a tighter verification of bus bridge operations can be accomplished.

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