Bus bridge interface system

Details Bus bridge interface system Bus bridge interface system

2001-08-17

2004-12-07

Dang, Khanh (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S052000, C710S060000

Reexamination Certificate

active

06829669

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is micro-controllers, which are widely applied in complex computer systems having multiple busses. Multiple bus systems must provide bus controllers to allow for coherent and collision-free communication between the separate buses. Micro-controllers used for this purpose provide bus arbitration which determines, at a given time, which device has control of the bus in question. The present invention describes a crucial device element in the implementation of multiple bus micro-controllers, the bus bridge interface system.
BACKGROUND OF THE INVENTION
As computer systems have grown more complex, it has become common to employ multiple processors and a wide variety of peripheral devices to transfer data within a chip and from the chip to external devices and vice versa. Such systems almost always have a multiple set of busses separating, for convenience and performance reasons, the communication between similar devices. Multiple bus systems must provide bus controllers to allow for coherent and collision-free communication between separate buses. Micro-controllers are used for this purpose and they provide bus arbitration which determines, at a given time, which device has control of the bus in question.
A prominent standard bus system has emerged for high performance micro-controller designs. The Advanced Micro-controller Bus Architecture System AMBA has been defined by Advanced RISC Machines (ARM) Ltd. (Cambridge, U.K.) and is described in U.S. Pat. No. 5,740,461, dated Apr. 14, 1998. Computer systems of a CISC variety are complex instruction set computers and have total backward compatibility requirements over all versions. RISC (reduced instruction set computer) systems, by contrast, are designed to have simple instruction sets and maximized efficiency of operation. Complex operations are accomplished in RISC machines as well, but they are achieved by using combinations of simple instructions. The RISC machines of ARM Ltd. forming the AMBA architecture are of primary interest here.
The standard AMBA has two main busses, a high performance AHB bus and a peripheral bus APB of more moderate performance. The AHB bus is the main memory bus and contains RAM and an external memory controller. In this basic system definition, if a high performance peripheral is required that will transfer large amounts of data, this peripheral is also placed on the high performance AHB bus. This decreases system performance, however, because the central processor unit (CPU) cannot have access to memory when the peripheral has control of the bus.
Advanced RISC Machines Ltd (ARM) has proposed an efficient arbitration scheme and split transfers to allow the CPU and the high performance peripheral to share bus time of the single AHB bus. ARM has also proposed use of a second bus for isolation and using a single arbiter. This proposal still allows only one transaction to progress at a given time period.
SUMMARY OF THE INVENTION
This invention describes an advanced high performance bus bridge, also known as AHB-to-HTB (High performance data Transfer Bus) bus bridge. The AHB-to-HTB bus bridge of this invention provides a means for the interfacing of two separate AHB-style busses allowing communication between them. and securing data integrity. Since these busses have different characteristics, one for CPU support and the other for support of a large amount of data transfer by a single peripheral, the bus bridge is defined with clear master-slave protocol.
The AHB-to-HTB bus bridge is a slave to the memory AHB bus and a master on the high performance data transfer bus, called the HTB bus. The HTB bus is also an AHB bus in timing and protocol. The AHB-to-HTB bus bridge contains all the slave AHB bus signals on the memory bus side but will generate the master AHB signals on the high performance data transfer bus side. The AHB-to-HTB bus bridge will also generate timing to guarantee data integrity between the two AHB-style busses. When a memory bus master wishes to either read from or write data to the high performance data transfer bus, the AHB-to-HTB bus bridge creates timing conditions to prevent read-after-write (RAW) hazards and write-after-read (WAR) hazards due to potential delays induced in bus synchronization and arbitration.


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