Bus bridge including first and second memory areas...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

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Details

C710S310000, C710S112000, C710S060000, C710S039000, C710S029000

Reexamination Certificate

active

06954820

ABSTRACT:
A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.

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patent: 6795886 (2004-09-01), Nguyen
patent: 05-002557 (1993-01-01), None
patent: 05-173933 (1993-07-01), None
patent: 10-254817 (1998-09-01), None

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