Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-03-10
2004-04-27
Myers, Paul R. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S301000
Reexamination Certificate
active
06728822
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an improvement of a bus bridge circuit for use in an information processing system (e.g., personal computer) with a plurality of buses, wherein the bus bridge circuit (e.g., CardBus controller) is connected between a primary bus (e.g., PCI bus) that is directly inaccessible to a user and a secondary bus (e.g., CardBus) that is directly accessible to a user. More specifically, this invention is arranged to add a logic circuit for implementing a special mode called “passthrough” to a bus bridge circuit, thereby enabling to perform nondestructive inspections (tests) of transactions on the primary bus from a connector or a slot of the bus bridge circuit.
BACKGROUND OF THE INVENTION
In case of performing a failure analysis of a personal computer (hereafter abbreviated to “PC”) at an arbitrary time during its development/production/operational phase, a PCI bus analyzer or exerciser is often used for inspecting transactions on a (primary) PCI bus as a system bus of the PC to investigate a failure mode.
Incidentally, as a PCI bus analyzer or exerciser that is usable with this invention, there is a “32/64 Bits, PCI Exerciser & Analyzer System” commercially available from Hewlett Packard Corp., which is a member of the family called “HP E2920 Computer Verification Tool, PCI Series”.
It is important to inspect transactions on a PCI bus, since every I/O transfer or memory transfer within a PC is performed via a host-PCI bridge and, thus, a PCI bus is involved in all transactions. In the following, backgrounds of transaction inspections will be briefly described.
As well known in the art, those signal lines that are required to get hold of basic data transfers on a PCI bus include at least forty-two signal lines, listed below, among a larger number of signal lines that are common to one or more peripheral devices connected to the PCI bus.
AD[31:0] (Address/Data)
CLK (Clock)
C/BE[3:0]# (Bus Command/Byte Enable)
FRAME# (Cycle Frame)
IRDY# (Initiator Ready)
TRDY# (Target Ready)
DEVSEL# (Device Select)
REQ# (Request)
GNT# (Grant)□□
STOP# (Stop) Note that a signal line with a symbol “#” is negative logic, i.e., low level=active.
In
FIG. 1
, there is schematically shown three normal transactions (bus cycles) on a PCI bus, which can be observed through bus signals appearing on these signal lines. For the purpose of estimating that any one of the transactions would be abnormal and, thus, there would be a failure within a PC under inspection, a PCI bus analyzer or the like is widely used: (1) to detect such a condition that the TRDY# signal line is not activated in synchronism with the currently active IRDY# signal line; and (2) to visually confirm any inequality between data on the AD[31:0] signal lines and predicted data, which was previously programmed.
Incidentally, in actual environments, physical conditions such as loads of a PCI bus (e.g., the number of PCI devices connected thereto) or effective line lengths may vary from one to another. Thus, it is difficult to precisely measure wave forms of signals on a PCI bus. However, even so, it is possible to get an entire image of each transaction on a PCI bus. Also, from such an entire image, it is possible to envision abnormality of each transaction to the extent that the purpose of inspection can be fully accomplished.
In
FIG. 2
, there is shown a schematic configuration of a desktop PC. In this desktop PC, optional slots or PCI connectors
22
are directly connected to a PCI bus
20
as usual. Accordingly, if a PCI bus analyzer or the like is connected to either one of PCI connectors
22
, transactions on PCI bus
20
can be inspected in an easier manner. However, for a desktop PC of the special type that has no PCI connector and/or a desktop PC that has no unused PCI connector, such an approach cannot be adopted as it is.
On the other hand, a notebook PC (hereafter abbreviated to “note PC”) has a limitation on its physical size. For this reason, a note PC of conventional type does not have a PCI connector as provided in a desktop PC. Stated in another way, a PCI bus of such a note PC is closed therein. Accordingly, in order to inspect transactions on a PCI bus, it becomes necessary to do cumbersome work, which includes disassembling of a note PC's system unit and outwardly extending those signal lines that are required for inspecting the transactions. Apparently, this is a crucial factor detrimental to efficiency of the inspection process.
In a note PC of the special type shown in
FIG. 3
, one or more tabs are provided at a card edge
34
on a main board
32
so that transactions on a PCI bus
30
can be inspected through the tabs. If a PCI bus analyzer or the like is connected to the card edge
34
, transactions on PCI bus
30
can be inspected in an easier manner at the main board
32
. Note in this respect, however, that the card edge
34
is made inaccessible to an outside user, thereby to avoid occurrence of any accidental event such as short-circuit or the like. Thus, in the form of a product incorporating the main board
32
, there is no way to readily access the card edge
34
and, therefore, transactions on PCI bus
30
cannot be inspected without disassembling the note PC's system unit.
In view of the aforesaid problems of the prior art, it is an object of this invention to improve a bus bridge circuit for use in an information processing system with a plurality of buses, wherein the bus bridge circuit is connected between a primary bus that is not directly accessible to a user and a secondary bus that is directly accessible to a user.
It is another object of this invention to add a logic circuit for implementing a special mode called “passthrough” to a bus bridge circuit, thereby enabling nondestructive inspections of transactions on the primary bus from a connector or a slot of the bus bridge circuit.
It is another object of this invention to provide an information processing system that has the aforesaid improved bus bridge circuit.
SUMMARY OF THE INVENTION
The foregoing and other objects of the invention are realized by system including a bus bridge circuit connected between a primary bus which is not directly accessible to a user and a secondary bus that is directly accessible to a user. The inventors herein have discerned that a number of note PCs are provided with CardBus controllers (alternatively called “PC card controller” or “PCI-CardBus bridge”), which are freely accessible to users. In particular, the present inventors have discerned that a secondary bus of a CardBus controller (i.e., CardBus) has been designed based on the architecture of a PCI bus and, hence, signals on a PCI bus may be easily inspected through a CardBus as they are.
A first aspect of this invention in accordance with these findings resides in a bus bridge circuit for use in an information processing system having a primary bus that is directly inaccessible to a user, one or more peripheral devices connected to the said primary bus, and a secondary bus that is directly accessible to a user, comprising: a control input means for switching operation modes of said bus bridge circuit, which is connected between said primary bus and said secondary bus; and a bypass path provided between an input side and an output side of said bus bridge circuit; whereby in case that a passthrough mode signal from said control input means exhibits an inactive state, said bus bridge circuit is enabled for operation and said bypass path is disabled for operation, thereby to cause said bus bridge circuit to be operated in its normal mode; and in another case that the passthrough mode signal from said control input means exhibits an active state, said bus bridge circuit is disabled for operation and said bypass path is enabled for operation, thereby to cause predetermined bus signals of a plurality of bus signals on said primary bus to be output on said secondary bus as they are via said bypass path.
In the first aspect, i
Hanami Hidenobu
Komiyama Hirohide
Sugawara Takashi
Dougherty Anne V.
Myers Paul R.
Percello Louis H.
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