Bus bridge circuit, bus connection system, and data error...

Details Bus bridge circuit, bus connection system, and data error... Bus bridge circuit, bus connection system, and data error...

2007-05-01

2007-05-01

Bonzo, Bryce P. (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C710S065000

Reexamination Certificate

active

10743140

ABSTRACT:
A bus bridge circuit is connected to first and second buses and performs data transfer between devices. In the bus bridge circuit, a new parity bit is generated from a parity bit generated by a first PCI device and from a byte enable signal from a second PCI device, and is transmitted to the second PCI device, together with read data from the first PCI device. Consequently even if the byte enable values are different on the primary-side and secondary-side buses, parity errors on the secondary-side bus can be correctly transmitted to the primary-side bus.

REFERENCES:
patent: 5155843 (1992-10-01), Stamm et al.
patent: 5404482 (1995-04-01), Stamm et al.
patent: 6934903 (2005-08-01), Keltcher et al.
patent: 6975752 (2005-12-01), Dixon et al.
patent: 2002/0046366 (2002-04-01), Ono
patent: 2004/0172581 (2004-09-01), Tamura et al.
patent: 9-081502 (1997-03-01), None

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